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* [dts] [PATCH] add coremask test plan
@ 2015-10-14  2:09 yongjie
  2015-10-14  2:09 ` [dts] [PATCH] add testsuite coremask yongjie
  0 siblings, 1 reply; 7+ messages in thread
From: yongjie @ 2015-10-14  2:09 UTC (permalink / raw)
  To: dts; +Cc: GuYongjie

From: GuYongjie <yongjiex.gu@intel.com>

Signed-off-by: GuYongjie <yongjiex.gu@intel.com>
---
 test_plans/coremask_test_plan.rst | 89 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 89 insertions(+)
 create mode 100644 test_plans/coremask_test_plan.rst

diff --git a/test_plans/coremask_test_plan.rst b/test_plans/coremask_test_plan.rst
new file mode 100644
index 0000000..0570221
--- /dev/null
+++ b/test_plans/coremask_test_plan.rst
@@ -0,0 +1,89 @@
+.. Copyright (c) <2010>, Intel Corporation
+   All rights reserved.
+   
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+   
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+   
+   - Neither the name of Intel Corporation nor the names of its
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+   
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+   COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Prerequisites
+=============
+
+This test will run in any machine able to run ``test``. No traffic will be sent.
+No extra needs for ports.
+
+
+Test Case: individual coremask
+==============================
+
+Launch ``test`` once per core, set the core mask for the core::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <One core mask> -n 4
+
+
+Verify: every time the application is launched the core is properly detected 
+and used.
+
+Stop ``test``.
+
+
+Test Case: big coremask
+=======================
+
+Launch ``test`` with a mask bigger than the available cores::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <128 bits mask> -n 4
+
+
+Verify: the application handles the mask properly and all the available cores 
+are detected and used.
+
+Stop ``test``.
+
+Test Case: all cores
+====================
+
+Launch ``test`` with all the available cores::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <All cores mask> -n 4
+
+
+Verify: all the cores have been detected and used by the application.
+
+Stop ``test``.
+
+Test Case: wrong coremask
+=========================
+
+Launch ``test`` with several wrong masks::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <Wrong mask> -n 4
+
+
+Verify: the application complains about the mask and does not start.
+
+Stop ``test``.
-- 
1.8.3.1

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [dts] [PATCH] add coremask test plan
@ 2015-10-22  7:26 yongjie
  2015-10-22  7:26 ` [dts] [PATCH] add testsuite coremask yongjie
  0 siblings, 1 reply; 7+ messages in thread
From: yongjie @ 2015-10-22  7:26 UTC (permalink / raw)
  To: dts; +Cc: Gu yongjie

From: Gu yongjie <yongjiex.gu@intel.com>


Signed-off-by: Gu yongjie <yongjiex.gu@intel.com>
---
 test_plans/coremask_test_plan.rst |   89 +++++++++++++++++++++++++++++++++++++
 1 files changed, 89 insertions(+), 0 deletions(-)
 create mode 100644 test_plans/coremask_test_plan.rst

diff --git a/test_plans/coremask_test_plan.rst b/test_plans/coremask_test_plan.rst
new file mode 100644
index 0000000..0570221
--- /dev/null
+++ b/test_plans/coremask_test_plan.rst
@@ -0,0 +1,89 @@
+.. Copyright (c) <2010>, Intel Corporation
+   All rights reserved.
+   
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+   
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in
+     the documentation and/or other materials provided with the
+     distribution.
+   
+   - Neither the name of Intel Corporation nor the names of its
+     contributors may be used to endorse or promote products derived
+     from this software without specific prior written permission.
+   
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+   FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+   COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+   INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+   (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+   SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+   HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+   STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+   OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Prerequisites
+=============
+
+This test will run in any machine able to run ``test``. No traffic will be sent.
+No extra needs for ports.
+
+
+Test Case: individual coremask
+==============================
+
+Launch ``test`` once per core, set the core mask for the core::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <One core mask> -n 4
+
+
+Verify: every time the application is launched the core is properly detected 
+and used.
+
+Stop ``test``.
+
+
+Test Case: big coremask
+=======================
+
+Launch ``test`` with a mask bigger than the available cores::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <128 bits mask> -n 4
+
+
+Verify: the application handles the mask properly and all the available cores 
+are detected and used.
+
+Stop ``test``.
+
+Test Case: all cores
+====================
+
+Launch ``test`` with all the available cores::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <All cores mask> -n 4
+
+
+Verify: all the cores have been detected and used by the application.
+
+Stop ``test``.
+
+Test Case: wrong coremask
+=========================
+
+Launch ``test`` with several wrong masks::
+
+    ./x86_64-default-linuxapp-gcc/app/test -c <Wrong mask> -n 4
+
+
+Verify: the application complains about the mask and does not start.
+
+Stop ``test``.
-- 
1.7.4.4

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [dts] [PATCH] add testsuite coremask
@ 2015-10-22  7:31 yongjie
  0 siblings, 0 replies; 7+ messages in thread
From: yongjie @ 2015-10-22  7:31 UTC (permalink / raw)
  To: dts; +Cc: Gu yongjie

From: Gu yongjie <yongjiex.gu@intel.com>


Signed-off-by: Gu yongjie <yongjiex.gu@intel.com>
---
 tests/TestSuite_coremask.py |  176 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 176 insertions(+), 0 deletions(-)
 create mode 100644 tests/TestSuite_coremask.py

diff --git a/tests/TestSuite_coremask.py b/tests/TestSuite_coremask.py
new file mode 100644
index 0000000..d1cc6e3
--- /dev/null
+++ b/tests/TestSuite_coremask.py
@@ -0,0 +1,176 @@
+# <COPYRIGHT_TAG>
+
+"""
+DPDK Test suite.
+
+Test coremask parsing in DPDK.
+
+"""
+
+import dts
+
+from exception import VerifyFailure
+from test_case import TestCase
+
+#
+#
+# Test class.
+#
+
+command_line = """./%s/app/test -c %s -n %d"""
+
+
+class TestCoremask(TestCase):
+
+    #
+    #
+    #
+    # Test cases.
+    #
+
+    def set_up_all(self):
+        """
+        Run at the start of each test suite.
+
+        Coremask Prerequisites.
+        """
+
+        self.port_mask = dts.create_mask(self.dut.get_ports(self.nic))
+        self.mem_channel = self.dut.get_memory_channels()
+
+        self.all_cores = self.dut.get_core_list("all")
+
+    def set_up(self):
+        """
+        Run before each test case.
+        """
+        pass
+
+    def test_individual_coremask(self):
+        """
+        Check coremask parsing for all the available cores one by one.
+        """
+
+        for core in self.all_cores:
+
+            core_mask = dts.create_mask([core])
+
+            command = command_line % (self.target, core_mask,
+                                      self.mem_channel)
+
+            out = self.dut.send_expect(command, "RTE>>", 10)
+
+            self.verify("EAL: Detected lcore %d as core" % core in out,
+                        "Core %d not detected" % core)
+
+            self.verify("EAL: Master lcore %d is ready" % core in out,
+                        "Core %d not ready" % core)
+
+            self.dut.send_expect("quit", "# ", 10)
+
+    def test_all_cores_coremask(self):
+        """
+        Check coremask parsing for all the cores at once.
+        """
+
+        core_mask = dts.create_mask(self.all_cores)
+
+        command = command_line % (self.target, core_mask, self.mem_channel)
+
+        out = self.dut.send_expect(command, "RTE>>", 10)
+
+        self.verify("EAL: Master lcore 0 is ready" in out,
+                    "Core 0 not ready")
+
+        self.verify("EAL: Detected lcore 0 as core" in out,
+                    "Core 0 not detected")
+
+        for core in self.all_cores[1:]:
+            self.verify("EAL: lcore %d is ready" % core in out,
+                        "Core %d not ready" % core)
+
+            self.verify("EAL: Detected lcore %d as core" % core in out,
+                        "Core %d not detected" % core)
+
+        self.dut.send_expect("quit", "# ", 10)
+
+    def test_big_coremask(self):
+        """
+        Check coremask parsing for more cores than available.
+        """
+
+        command_line = """./%s/app/test -c %s -n %d|tee out"""
+
+        # Default big coremask value 128
+        big_coremask_size = 128
+
+        try:
+            out = self.dut.send_expect("cat config/defconfig_%s" % self.target, "]# ", 10)
+            start_position = out.find('CONFIG_RTE_MAX_LCORE=')
+
+            if start_position > -1:
+                end_position = out.find('\n', start_position)
+                big_coremask_size = int(out[start_position + 21:end_position])
+
+                print "Detected CONFIG_RTE_MAX_LCORE=%d" % big_coremask_size
+        except:
+            print "Using default big coremask %d" % big_coremask_size
+
+        # Create a extremely big coremask
+        big_coremask = "0x"
+        for _ in range(0, big_coremask_size, 4):
+            big_coremask += "F"
+
+        command = command_line % (self.target, big_coremask, self.mem_channel)
+        try:
+            self.dut.send_expect(command, "RTE>>", 10)
+        except:
+            out = self.dut.send_expect("cat out", "# ")
+
+            self.verify("EAL: invalid coremask" in out,
+                    "Small core mask set")
+
+        self.verify("EAL: Detected lcore 0 as core" in out,
+                    "Core 0 not detected")
+
+        for core in self.all_cores[1:]:
+
+            self.verify("EAL: Detected lcore %d as core" % core in out,
+                        "Core %d not detected" % core)
+
+        self.dut.send_expect("quit", "# ", 10)
+
+    def test_wrong_coremask(self):
+        """
+        Check coremask parsing for wrong coremasks.
+        """
+
+        wrong_coremasks = ["GARBAGE", "0xJF", "0xFJF", "0xFFJ",
+                           "0xJ11", "0x1J1", "0x11J",
+                           "JF", "FJF", "FFJ",
+                           "J11", "1J1", "11J",
+                           "jf", "fjf", "ffj",
+                           "FF0x", "ff0x", "", "0x", "0"]
+
+        for coremask in wrong_coremasks:
+
+            command = command_line % (self.target, coremask, self.mem_channel)
+            try:
+                out = self.dut.send_expect(command, "# ", 5)
+                self.verify("EAL: invalid coremask" in out,
+                            "Wrong core mask (%s) accepted" % coremask)
+            except:
+                self.dut.send_expect("quit", "# ", 5)
+                raise VerifyFailure("Wrong core mask (%s) accepted" % coremask)
+
+    def tear_down(self):
+        """
+        Run after each test case.
+        """
+        self.dut.kill_all()
+
+    def tear_down_all(self):
+        """
+        Run after each test suite.
+        """
+        pass
-- 
1.7.4.4

^ permalink raw reply	[flat|nested] 7+ messages in thread
* [dts] [PATCH] add testsuite coremask
@ 2015-10-22  8:22 yongjie
  2015-10-23  1:03 ` Liu, Yong
  0 siblings, 1 reply; 7+ messages in thread
From: yongjie @ 2015-10-22  8:22 UTC (permalink / raw)
  To: dts; +Cc: Gu yongjie

From: Gu yongjie <yongjiex.gu@intel.com>



This test will launch application "test" with different core mask(individual,all_cores,big,wrong),
and verify that whether the "test" respond correctly.

Signed-off-by: Gu yongjie <yongjiex.gu@intel.com>
---
 tests/TestSuite_coremask.py |  176 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 176 insertions(+), 0 deletions(-)
 create mode 100644 tests/TestSuite_coremask.py

diff --git a/tests/TestSuite_coremask.py b/tests/TestSuite_coremask.py
new file mode 100644
index 0000000..d1cc6e3
--- /dev/null
+++ b/tests/TestSuite_coremask.py
@@ -0,0 +1,176 @@
+# <COPYRIGHT_TAG>
+
+"""
+DPDK Test suite.
+
+Test coremask parsing in DPDK.
+
+"""
+
+import dts
+
+from exception import VerifyFailure
+from test_case import TestCase
+
+#
+#
+# Test class.
+#
+
+command_line = """./%s/app/test -c %s -n %d"""
+
+
+class TestCoremask(TestCase):
+
+    #
+    #
+    #
+    # Test cases.
+    #
+
+    def set_up_all(self):
+        """
+        Run at the start of each test suite.
+
+        Coremask Prerequisites.
+        """
+
+        self.port_mask = dts.create_mask(self.dut.get_ports(self.nic))
+        self.mem_channel = self.dut.get_memory_channels()
+
+        self.all_cores = self.dut.get_core_list("all")
+
+    def set_up(self):
+        """
+        Run before each test case.
+        """
+        pass
+
+    def test_individual_coremask(self):
+        """
+        Check coremask parsing for all the available cores one by one.
+        """
+
+        for core in self.all_cores:
+
+            core_mask = dts.create_mask([core])
+
+            command = command_line % (self.target, core_mask,
+                                      self.mem_channel)
+
+            out = self.dut.send_expect(command, "RTE>>", 10)
+
+            self.verify("EAL: Detected lcore %d as core" % core in out,
+                        "Core %d not detected" % core)
+
+            self.verify("EAL: Master lcore %d is ready" % core in out,
+                        "Core %d not ready" % core)
+
+            self.dut.send_expect("quit", "# ", 10)
+
+    def test_all_cores_coremask(self):
+        """
+        Check coremask parsing for all the cores at once.
+        """
+
+        core_mask = dts.create_mask(self.all_cores)
+
+        command = command_line % (self.target, core_mask, self.mem_channel)
+
+        out = self.dut.send_expect(command, "RTE>>", 10)
+
+        self.verify("EAL: Master lcore 0 is ready" in out,
+                    "Core 0 not ready")
+
+        self.verify("EAL: Detected lcore 0 as core" in out,
+                    "Core 0 not detected")
+
+        for core in self.all_cores[1:]:
+            self.verify("EAL: lcore %d is ready" % core in out,
+                        "Core %d not ready" % core)
+
+            self.verify("EAL: Detected lcore %d as core" % core in out,
+                        "Core %d not detected" % core)
+
+        self.dut.send_expect("quit", "# ", 10)
+
+    def test_big_coremask(self):
+        """
+        Check coremask parsing for more cores than available.
+        """
+
+        command_line = """./%s/app/test -c %s -n %d|tee out"""
+
+        # Default big coremask value 128
+        big_coremask_size = 128
+
+        try:
+            out = self.dut.send_expect("cat config/defconfig_%s" % self.target, "]# ", 10)
+            start_position = out.find('CONFIG_RTE_MAX_LCORE=')
+
+            if start_position > -1:
+                end_position = out.find('\n', start_position)
+                big_coremask_size = int(out[start_position + 21:end_position])
+
+                print "Detected CONFIG_RTE_MAX_LCORE=%d" % big_coremask_size
+        except:
+            print "Using default big coremask %d" % big_coremask_size
+
+        # Create a extremely big coremask
+        big_coremask = "0x"
+        for _ in range(0, big_coremask_size, 4):
+            big_coremask += "F"
+
+        command = command_line % (self.target, big_coremask, self.mem_channel)
+        try:
+            self.dut.send_expect(command, "RTE>>", 10)
+        except:
+            out = self.dut.send_expect("cat out", "# ")
+
+            self.verify("EAL: invalid coremask" in out,
+                    "Small core mask set")
+
+        self.verify("EAL: Detected lcore 0 as core" in out,
+                    "Core 0 not detected")
+
+        for core in self.all_cores[1:]:
+
+            self.verify("EAL: Detected lcore %d as core" % core in out,
+                        "Core %d not detected" % core)
+
+        self.dut.send_expect("quit", "# ", 10)
+
+    def test_wrong_coremask(self):
+        """
+        Check coremask parsing for wrong coremasks.
+        """
+
+        wrong_coremasks = ["GARBAGE", "0xJF", "0xFJF", "0xFFJ",
+                           "0xJ11", "0x1J1", "0x11J",
+                           "JF", "FJF", "FFJ",
+                           "J11", "1J1", "11J",
+                           "jf", "fjf", "ffj",
+                           "FF0x", "ff0x", "", "0x", "0"]
+
+        for coremask in wrong_coremasks:
+
+            command = command_line % (self.target, coremask, self.mem_channel)
+            try:
+                out = self.dut.send_expect(command, "# ", 5)
+                self.verify("EAL: invalid coremask" in out,
+                            "Wrong core mask (%s) accepted" % coremask)
+            except:
+                self.dut.send_expect("quit", "# ", 5)
+                raise VerifyFailure("Wrong core mask (%s) accepted" % coremask)
+
+    def tear_down(self):
+        """
+        Run after each test case.
+        """
+        self.dut.kill_all()
+
+    def tear_down_all(self):
+        """
+        Run after each test suite.
+        """
+        pass
-- 
1.7.4.4

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2015-10-23  1:01 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2015-10-14  2:09 [dts] [PATCH] add coremask test plan yongjie
2015-10-14  2:09 ` [dts] [PATCH] add testsuite coremask yongjie
2015-10-14  8:24   ` Qiu, Michael
2015-10-22  7:26 [dts] [PATCH] add coremask test plan yongjie
2015-10-22  7:26 ` [dts] [PATCH] add testsuite coremask yongjie
2015-10-22  7:31 yongjie
2015-10-22  8:22 yongjie
2015-10-23  1:03 ` Liu, Yong

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