From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 6C8C293E8 for ; Thu, 22 Oct 2015 09:30:39 +0200 (CEST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga103.fm.intel.com with ESMTP; 22 Oct 2015 00:30:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,181,1444719600"; d="scan'208";a="832379248" Received: from unknown (HELO dpdk-fedora20.icx.intel.com) ([10.238.55.12]) by orsmga002.jf.intel.com with ESMTP; 22 Oct 2015 00:30:37 -0700 From: yongjie To: dts@dpdk.org Date: Thu, 22 Oct 2015 15:26:15 +0800 Message-Id: <1445498775-12590-2-git-send-email-yongjiex.gu@intel.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1445498775-12590-1-git-send-email-yongjiex.gu@intel.com> References: <1445498775-12590-1-git-send-email-yongjiex.gu@intel.com> Cc: GuYongjie Subject: [dts] [PATCH] add testsuite coremask X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Oct 2015 07:30:40 -0000 From: GuYongjie Signed-off-by: GuYongjie --- tests/TestSuite_coremask.py | 189 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) create mode 100644 tests/TestSuite_coremask.py diff --git a/tests/TestSuite_coremask.py b/tests/TestSuite_coremask.py new file mode 100644 index 0000000..3520a9c --- /dev/null +++ b/tests/TestSuite_coremask.py @@ -0,0 +1,189 @@ +# + +""" +DPDK Test suite. + +Test coremask parsing in DPDK. + +""" + +import dts + +from exception import VerifyFailure +from test_case import TestCase + +# +# +# Test class. +# + +command_line = """./%s/app/test -c %s -n %d""" + + +class TestCoremask(TestCase): + + # + # + # + # Test cases. + # + + def set_up_all(self): + """ + Run at the start of each test suite. + + Coremask Prerequisites. + """ + + self.port_mask = dts.create_mask(self.dut.get_ports(self.nic)) + self.mem_channel = self.dut.get_memory_channels() + + self.all_cores = self.dut.get_core_list("all") + + def set_up(self): + """ + Run before each test case. + """ + pass + + def test_individual_coremask(self): + """ + Check coremask parsing for all the available cores one by one. + """ + + for core in self.all_cores: + + core_mask = dts.create_mask([core]) + + command = command_line % (self.target, core_mask, + self.mem_channel) + + out = self.dut.send_expect(command, "RTE>>", 10) + + #self.verify("EAL: coremask after trimmed is %s" % core_mask[2:] in out, + # "Wrong core mask set") + + self.verify("EAL: Detected lcore %d as core" % core in out, + "Core %d not detected" % core) + + self.verify("EAL: Master lcore %d is ready" % core in out, + "Core %d not ready" % core) + + self.dut.send_expect("quit", "# ", 10) + + def test_all_cores_coremask(self): + """ + Check coremask parsing for all the cores at once. + """ + + core_mask = dts.create_mask(self.all_cores) + + command = command_line % (self.target, core_mask, self.mem_channel) + + out = self.dut.send_expect(command, "RTE>>", 10) + #self.verify("EAL: coremask after trimmed is %s" % core_mask[2:] in out, + # "Wrong core mask set") + + self.verify("EAL: Master lcore 0 is ready" in out, + "Core 0 not ready") + + self.verify("EAL: Detected lcore 0 as core" in out, + "Core 0 not detected") + + for core in self.all_cores[1:]: + self.verify("EAL: lcore %d is ready" % core in out, + "Core %d not ready" % core) + + self.verify("EAL: Detected lcore %d as core" % core in out, + "Core %d not detected" % core) + + self.dut.send_expect("quit", "# ", 10) + + def test_big_coremask(self): + """ + Check coremask parsing for more cores than available. + """ + + command_line = """./%s/app/test -c %s -n %d|tee out""" + + # Default big coremask value 128 + big_coremask_size = 128 + + try: + out = self.dut.send_expect("cat config/defconfig_%s" % self.target, "]# ", 10) + start_position = out.find('CONFIG_RTE_MAX_LCORE=') + + if start_position > -1: + end_position = out.find('\n', start_position) + big_coremask_size = int(out[start_position + 21:end_position]) + + print "Detected CONFIG_RTE_MAX_LCORE=%d" % big_coremask_size + except: + print "Using default big coremask %d" % big_coremask_size + + # Create a extremely big coremask + big_coremask = "0x" + for _ in range(0, big_coremask_size, 4): + big_coremask += "F" + + command = command_line % (self.target, big_coremask, self.mem_channel) + try: + self.dut.send_expect(command, "RTE>>", 10) + except: + out = self.dut.send_expect("cat out", "# ") + + self.verify("EAL: invalid coremask" in out, + "Small core mask set") + + #self.verify("EAL: coremask after trimmed is %s" % big_coremask[2:] in out, + # "Wrong core mask set") + + #self.verify("EAL: Master lcore 0 is ready" in out, + # "Core 0 not ready") + + self.verify("EAL: Detected lcore 0 as core" in out, + "Core 0 not detected") + + for core in self.all_cores[1:]: + #self.verify("EAL: lcore %d is ready" % core in out, + # "Core %d not ready" % core) + + self.verify("EAL: Detected lcore %d as core" % core in out, + "Core %d not detected" % core) + + self.dut.send_expect("quit", "# ", 10) + + def test_wrong_coremask(self): + """ + Check coremask parsing for wrong coremasks. + """ + + wrong_coremasks = ["GARBAGE", "0xJF", "0xFJF", "0xFFJ", + "0xJ11", "0x1J1", "0x11J", + "JF", "FJF", "FFJ", + "J11", "1J1", "11J", + "jf", "fjf", "ffj", + "FF0x", "ff0x", "", "0x", "0"] + + for coremask in wrong_coremasks: + + command = command_line % (self.target, coremask, self.mem_channel) + try: + out = self.dut.send_expect(command, "# ", 5) + self.verify("EAL: invalid coremask" in out, + "Wrong core mask (%s) accepted" % coremask) + except: + self.dut.send_expect("quit", "# ", 5) + raise VerifyFailure("Wrong core mask (%s) accepted" % coremask) + + def tear_down(self): + """ + Run after each test case. + """ + self.dut.kill_all() + + def tear_down_all(self): + """ + Run after each test suite. + """ + pass -- 1.8.3.1