From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id CD1BE2965 for ; Tue, 12 Apr 2016 03:38:10 +0200 (CEST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP; 11 Apr 2016 18:38:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,471,1455004800"; d="scan'208";a="684691030" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by FMSMGA003.fm.intel.com with ESMTP; 11 Apr 2016 18:38:09 -0700 Received: from shecgisg003.sh.intel.com (shecgisg003.sh.intel.com [10.239.29.90]) by shvmail01.sh.intel.com with ESMTP id u3C1c7Ft009178; Tue, 12 Apr 2016 09:38:07 +0800 Received: from shecgisg003.sh.intel.com (localhost [127.0.0.1]) by shecgisg003.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u3C1c5Ak007221; Tue, 12 Apr 2016 09:38:07 +0800 Received: (from hengdinx@localhost) by shecgisg003.sh.intel.com (8.13.6/8.13.6/Submit) id u3C1c5aT007216; Tue, 12 Apr 2016 09:38:05 +0800 From: Ding Heng To: dts@dpdk.org Cc: Ding Heng Date: Tue, 12 Apr 2016 09:38:01 +0800 Message-Id: <1460425081-7185-1-git-send-email-hengx.ding@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dts] [PATCH] dut.py: sort port list to ensure RRC nics will be configured correctly X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Apr 2016 01:38:11 -0000 Signed-off-by: Ding Heng diff --git a/framework/dut.py b/framework/dut.py index bd437cb..291fef0 100644 --- a/framework/dut.py +++ b/framework/dut.py @@ -627,6 +627,20 @@ class Dut(Crb): """ Scan ports information or just read it from cache file. """ + #sort ports and ensure that first port of RRC nics will be + #initialized first + sorted_ports = [] + ports_cfg = self.conf.get_ports_config() + for port_cfg_all in ports_cfg.keys(): + if 'tp_path' in ports_cfg[port_cfg_all].keys(): + for port in self.pci_devices_info: + sorted_port = [port] + if port_cfg_all in port: + self.pci_devices_info.remove(port) + for i in self.pci_devices_info: + sorted_port.append(i) + self.pci_devices_info = sorted_port + if self.read_cache: self.load_serializer_ports() self.scan_ports_cached() -- 1.9.3