From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 2090D2C37 for ; Thu, 4 Aug 2016 07:38:32 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 03 Aug 2016 22:38:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,469,1464678000"; d="scan'208";a="1034814577" Received: from shvmail01.sh.intel.com ([10.239.29.42]) by fmsmga002.fm.intel.com with ESMTP; 03 Aug 2016 22:38:32 -0700 Received: from shecgisg003.sh.intel.com (shecgisg003.sh.intel.com [10.239.29.90]) by shvmail01.sh.intel.com with ESMTP id u745cU1P003405; Thu, 4 Aug 2016 13:38:30 +0800 Received: from shecgisg003.sh.intel.com (localhost [127.0.0.1]) by shecgisg003.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP id u745cRu0012727; Thu, 4 Aug 2016 13:38:30 +0800 Received: (from yliu84x@localhost) by shecgisg003.sh.intel.com (8.13.6/8.13.6/Submit) id u745cRvF012723; Thu, 4 Aug 2016 13:38:27 +0800 From: Marvin Liu To: dts@dpdk.org Cc: Marvin Liu Date: Thu, 4 Aug 2016 13:38:15 +0800 Message-Id: <1470289102-12677-3-git-send-email-yong.liu@intel.com> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1470289102-12677-1-git-send-email-yong.liu@intel.com> References: <1470289102-12677-1-git-send-email-yong.liu@intel.com> Subject: [dts] [PATCH 2/9] framework config: add concept for dut board X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Aug 2016 05:38:33 -0000 Signed-off-by: Marvin Liu diff --git a/framework/config.py b/framework/config.py index 8d564a6..6c3a3b0 100644 --- a/framework/config.py +++ b/framework/config.py @@ -187,7 +187,7 @@ class PortConf(UserConf): class CrbsConf(UserConf): - DEF_CRB = {'IP': '', 'name': 'CrownPassCRB1', 'user': '', + DEF_CRB = {'IP': '', 'board': 'default', 'user': '', 'pass': '', 'tester IP': '', 'tester pass': '', IXIA: None, 'memory channels': 4, 'bypass core0': True} @@ -236,6 +236,8 @@ class CrbsConf(UserConf): crb['bypass core0'] = True else: crb['bypass core0'] = False + elif key == 'board': + crb['board'] = value self.crbs_cfg.append(crb) return self.crbs_cfg -- 1.9.3