From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id 973121B38B for ; Mon, 13 Nov 2017 16:08:23 +0100 (CET) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Nov 2017 07:08:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,389,1505804400"; d="scan'208";a="172978845" Received: from yuweizh1-mobl2.ccr.corp.intel.com ([10.255.24.211]) by orsmga005.jf.intel.com with ESMTP; 13 Nov 2017 07:08:21 -0800 From: Yuwei Zhang To: dts@dpdk.org Cc: Yuwei Zhang Date: Mon, 13 Nov 2017 23:08:18 +0800 Message-Id: <20171113150818.7960-1-yuwei1.zhang@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 Subject: [dts] [PATCH V2] Add a function used to verify keep packets' order feature X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Nov 2017 15:08:25 -0000 Signed-off-by: Yuwei Zhang --- framework/etgen.py | 74 +++++++++++++++++++++++------------------------------ framework/tester.py | 7 +++++ 2 files changed, 39 insertions(+), 42 deletions(-) diff --git a/framework/etgen.py b/framework/etgen.py index b19ae84..373e420 100644 --- a/framework/etgen.py +++ b/framework/etgen.py @@ -558,6 +558,38 @@ class IxiaPacketGenerator(SSHConnection): rxPortlist, txPortlist = self._configure_everything(port_list, rate_percent) return self.get_transmission_results(rxPortlist, txPortlist, delay) + def is_packet_ordered(self, port_list, delay): + rxPortlist, txPortlist = self.prepare_port_list(port_list) + self.prepare_ixia_for_transmission(txPortlist, rxPortlist) + self.send_expect('port config -receiveMode [expr $::portCapture|$::portRxFirstTimeStamp|$::portRxSequenceChecking|$::portRxModeWidePacketGroup]', '%') + self.send_expect('port config -autonegotiate true', '%') + self.send_expect('ixWritePortsToHardware portList', '%') + self.send_expect('set streamId 1', '%') + self.send_expect('stream setDefault', '%') + self.send_expect('ixStartPortPacketGroups %d %d %d' % (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%') + self.send_expect('ixStartTransmit portList', '%') + self.send_expect('after 1000 * %d' % delay, '%') + self.send_expect('ixStopTransmit portList', '%') + self.send_expect('ixStopPortPacketGroups %d %d %d' % (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%') + self.send_expect('after 1000 * %d' % delay, '%') + self.send_expect('packetGroupStats get %d %d %d 1 1' % (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%') + self.send_expect('packetroupStats getGroup 1', '%') + self.send_expect('set reverseSequenceError [packetGroupStats cget -reverseSequenceError]]', '%') + output = self.send_expect('puts $reverseSequenceError', '%') + return int(output[:-2]) + def _configure_everything(self, port_list, rate_percent, latency=False): """ Prepare and configure IXIA ports for performance test. diff --git a/framework/tester.py b/framework/tester.py index 9208b0e..1c854d7 100644 --- a/framework/tester.py +++ b/framework/tester.py @@ -502,6 +502,13 @@ class Tester(Crb): return None return self.packet_gen.throughput(portList, rate_percent) + def verify_packet_order(self, portList, delay): + if self.check_port_list(portList, 'ixia'): + return self.ixia_packet_gen.is_packet_ordered(portList, delay) + else: + self.logger.warning("Only ixia port support check verify packet order function") + return False + def run_rfc2544(self, portlist, delay=120, permit_loss_rate=0): """ test_rate: the line rate we are going to test. -- 2.14.1.windows.1