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From: Yuwei Zhang <yuwei1.zhang@intel.com>
To: dts@dpdk.org
Cc: Yuwei Zhang <yuwei1.zhang@intel.com>
Subject: [dts] [PATCH V3] Add a function used to verify keep packets' order feature
Date: Mon, 20 Nov 2017 11:36:53 +0800	[thread overview]
Message-ID: <20171120033653.13576-1-yuwei1.zhang@intel.com> (raw)

add a description to the function, remove the unnecessary sleep code and portRxFirstTimeStamp mode, portCapture is necessary because ixia need to check sequence in the captured packets.

Signed-off-by: Yuwei Zhang <yuwei1.zhang@intel.com>
---
 framework/etgen.py  | 74 +++++++++++++++++++++++------------------------------
 framework/tester.py |  7 +++++
 2 files changed, 39 insertions(+), 42 deletions(-)

diff --git a/framework/etgen.py b/framework/etgen.py
index b19ae84..373e420 100644
--- a/framework/etgen.py
+++ b/framework/etgen.py
@@ -558,6 +558,38 @@ class IxiaPacketGenerator(SSHConnection):
         rxPortlist, txPortlist = self._configure_everything(port_list, rate_percent)
         return self.get_transmission_results(rxPortlist, txPortlist, delay)
 
+    """
+    This function could be used to check the packets' order after some prcessing whether same as the receive sequence.
+    Please notice that this function only support single-stream mode.
+    """
+    def is_packet_ordered(self, port_list, delay):
+        rxPortlist, txPortlist = self.prepare_port_list(port_list)
+        self.prepare_ixia_for_transmission(txPortlist, rxPortlist)
+        self.send_expect('port config -receiveMode [expr $::portCapture|$::portRxSequenceChecking|$::portRxModeWidePacketGroup]', '%')
+        self.send_expect('port config -autonegotiate true', '%')
+        self.send_expect('ixWritePortsToHardware portList', '%')
+        self.send_expect('set streamId 1', '%')
+        self.send_expect('stream setDefault', '%')
+        self.send_expect('ixStartPortPacketGroups %d %d %d' % (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%')
+        self.send_expect('ixStartTransmit portList', '%')
+        self.send_expect('after 1000 * %d' % delay, '%')
+        self.send_expect('ixStopTransmit portList', '%')
+        self.send_expect('ixStopPortPacketGroups %d %d %d' % (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%')
+        self.send_expect('packetGroupStats get %d %d %d 1 1' % (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%')
+        self.send_expect('packetroupStats getGroup 1', '%')
+        self.send_expect('set reverseSequenceError [packetGroupStats cget -reverseSequenceError]]', '%')
+        output = self.send_expect('puts $reverseSequenceError', '%')
+        return int(output[:-2])
+
     def _configure_everything(self, port_list, rate_percent, latency=False):
         """
         Prepare and configure IXIA ports for performance test.

diff --git a/framework/tester.py b/framework/tester.py
index 9208b0e..1c854d7 100644
--- a/framework/tester.py
+++ b/framework/tester.py
@@ -502,6 +502,13 @@ class Tester(Crb):
             return None
         return self.packet_gen.throughput(portList, rate_percent)
 
+    def verify_packet_order(self, portList, delay):
+        if self.check_port_list(portList, 'ixia'):
+            return self.ixia_packet_gen.is_packet_ordered(portList, delay)
+        else:
+            self.logger.warning("Only ixia port support check verify packet order function")
+            return False
+
     def run_rfc2544(self, portlist, delay=120, permit_loss_rate=0):
         """
         test_rate: the line rate we are going to test.
-- 
2.14.1.windows.1

             reply	other threads:[~2017-11-20  3:36 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-20  3:36 Yuwei Zhang [this message]
2017-11-20 13:08 ` Liu, Yong

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