From: yufengmx <yufengx.mo@intel.com>
To: dts@dpdk.org, zhaoyan.chen@intel.com, lijuan.tu@intel.com
Cc: yufengmx <yufengx.mo@intel.com>
Subject: [dts] [PATCH V1 1/1] [next]dts/pktgen: add support pci address mapping sytle
Date: Mon, 23 Sep 2019 14:51:38 +0800 [thread overview]
Message-ID: <20190923065138.8343-2-yufengx.mo@intel.com> (raw)
In-Reply-To: <20190923065138.8343-1-yufengx.mo@intel.com>
make pktgen trex port mapping to be compatible with pci address mapping sytle.
Signed-off-by: yufengmx <yufengx.mo@intel.com>
---
framework/dut.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/framework/dut.py b/framework/dut.py
index fc4a2e6..c2ed0f1 100644
--- a/framework/dut.py
+++ b/framework/dut.py
@@ -986,7 +986,8 @@ class Dut(Crb):
if peer is not None:
for remotePort in range(len(self.tester.ports_info)):
if self.tester.ports_info[remotePort]['type'].lower() == 'trex':
- if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower():
+ if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower() or \
+ self.tester.ports_info[remotePort]['pci'].lower() == peer.lower():
hits[remotePort] = True
self.ports_map[dutPort] = remotePort
break
--
2.21.0
next prev parent reply other threads:[~2019-09-23 6:50 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 6:51 [dts] [PATCH V1 0/1] " yufengmx
2019-09-23 6:51 ` yufengmx [this message]
2019-09-23 6:57 ` [dts] [PATCH V1 1/1] " Mo, YufengX
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