From: lingwei <weix.ling@intel.com>
To: dts@dpdk.org
Cc: lingwei <weix.ling@intel.com>
Subject: [dts] [dts 2/6] test_plans/nic_single_core_perf_test_plan: update test plan to sync with testcase
Date: Wed, 2 Sep 2020 14:14:56 +0000 [thread overview]
Message-ID: <20200902141500.92740-3-weix.ling@intel.com> (raw)
In-Reply-To: <20200902141500.92740-1-weix.ling@intel.com>
Signed-off-by: lingwei <weix.ling@intel.com>
---
test_plans/nic_single_core_perf_test_plan.rst | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/test_plans/nic_single_core_perf_test_plan.rst b/test_plans/nic_single_core_perf_test_plan.rst
index 4157c31..c78abad 100644
--- a/test_plans/nic_single_core_perf_test_plan.rst
+++ b/test_plans/nic_single_core_perf_test_plan.rst
@@ -62,6 +62,13 @@ Prerequisites
2 TG 25g ports for FVL25G ports
4 TG 10g ports for 4 NNT10G ports
+
+4. Case config::
+ For FVL40g, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=y"
+ in ./config/common_base and re-build DPDK.
+
+ For FVL25G, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_ICE_16BYTE_RX_DESC=y"
+ in ./config/common_base and re-build DPDK.
Test Case : Single Core Performance Measurement
===============================================
--
2.17.1
next prev parent reply other threads:[~2020-09-02 6:17 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-02 14:14 [dts] [PATCH V1 0/6] " lingwei
2020-09-02 14:14 ` [dts] [dts 1/6] tests/TestSuite_vmdq_dcb: set dpdk config before build by meson and use api to get app name lingwei
2020-09-02 14:14 ` lingwei [this message]
2020-09-02 14:14 ` [dts] [dts 3/6] test_plans/pmd_test_plan: update test plan to sync with testcase lingwei
2020-09-02 14:14 ` [dts] [dts 4/6] test_plans/vmdq_test_plan: " lingwei
2020-09-02 14:14 ` [dts] [dts 5/6] test_plans/ptpclient_test_plan: " lingwei
2020-09-02 14:15 ` [dts] [dts 6/6] test_plans/vf_l3fwd_test_plan: " lingwei
2020-09-07 5:19 ` [dts] [PATCH V1 0/6] " Ma, LihongX
2020-09-07 5:52 ` Ling, WeiX
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