* Re: [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551
2020-10-15 9:48 [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551 sunqin
@ 2020-10-15 5:14 ` Peng, Yuan
2020-10-15 7:04 ` Sun, QinX
2020-10-16 6:56 ` Ma, LihongX
2 siblings, 0 replies; 4+ messages in thread
From: Peng, Yuan @ 2020-10-15 5:14 UTC (permalink / raw)
To: Sun, QinX, dts; +Cc: Sun, QinX
Acked-by Peng, Yuan <yuan.peng@intel.com>
-----Original Message-----
From: dts <dts-bounces@dpdk.org> On Behalf Of sunqin
Sent: Thursday, October 15, 2020 5:49 PM
To: dts@dpdk.org
Cc: Sun, QinX <qinx.sun@intel.com>
Subject: [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551
According to dpdk commit cb97e595d9d3b316690c8d5ac688240d2ba1e551 to modify log validation for wrong action
Signed-off-by: sunqin <qinx.sun@intel.com>
---
test_plans/cvl_fdir_test_plan.rst | 8 ++++----
tests/TestSuite_cvl_fdir.py | 14 +++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/test_plans/cvl_fdir_test_plan.rst b/test_plans/cvl_fdir_test_plan.rst
index 0e1521f..740cb37 100644
--- a/test_plans/cvl_fdir_test_plan.rst
+++ b/test_plans/cvl_fdir_test_plan.rst
@@ -610,7 +610,7 @@ Note: there may be error message change.
get the message::
- Invalid input action: Invalid argument
+ 'error' in message
Discontinuous queues::
@@ -2939,7 +2939,7 @@ Subcase 1: invalid parameters of queue index
Failed to create flow, report message::
- Invalid queue for FDIR.: Invalid argument
+ 'error' in message
2. check there is no rule listed.
@@ -3053,7 +3053,7 @@ Subcase 6: conflicted rules
or::
- Invalid input action number: Invalid argument
+ 'error' in message
3. check there is only one rule listed.
@@ -3066,7 +3066,7 @@ Subcase 7: conflicted actions
Failed to create flow, report message::
- Invalid input action: Invalid argument
+ 'error' in message
2. check there is no rule listed.
diff --git a/tests/TestSuite_cvl_fdir.py b/tests/TestSuite_cvl_fdir.py index e5a9c71..fd005b3 100644
--- a/tests/TestSuite_cvl_fdir.py
+++ b/tests/TestSuite_cvl_fdir.py
@@ -2428,7 +2428,7 @@ class TestCVLFdir(TestCase):
check_stats=False, check_msg='Bad arguments')
self.validate_fdir_rule(
'flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 2 3 end / rss / end',
- check_stats=False, check_msg='Invalid input action number: Invalid argument')
+ check_stats=False, check_msg='error')
self.validate_fdir_rule(
'flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions passthru / mark id 4294967296 / end',
check_stats=False, check_msg='Bad arguments') @@ -2580,7 +2580,7 @@ class TestCVLFdir(TestCase):
def test_invalid_parameters_of_queue_index(self):
rule = "flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions queue index 64 / end"
out = self.dut.send_command(rule, timeout=1)
- self.verify("Invalid input action: Invalid argument" in out, "failed with output: %s" % out)
+ self.verify("error" in out, "failed with output: %s" % out)
self.check_fdir_rule(port_id=0, stats=False)
def test_invalid_parameters_of_rss_queues(self):
@@ -2588,11 +2588,11 @@ class TestCVLFdir(TestCase):
"flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 end / end",
"flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 0 end / end",
"flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues end / end"]
- self.create_fdir_rule(rule=rule1, check_stats=False, msg='Invalid input action: Invalid argument')
+ self.create_fdir_rule(rule=rule1, check_stats=False,
+ msg='error')
rule2 = 'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 5 end / end'
- self.create_fdir_rule(rule2, check_stats=False, msg='Invalid input action: Invalid argument')
+ self.create_fdir_rule(rule2, check_stats=False, msg='error')
rule3 = 'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 63 64 end / end'
- self.create_fdir_rule(rule3, check_stats=False, msg='Invalid input action: Invalid argument')
+ self.create_fdir_rule(rule3, check_stats=False, msg='error')
try:
# restart testpmd
self.dut.send_expect("quit", "# ") @@ -2655,13 +2655,13 @@ class TestCVLFdir(TestCase):
'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2021 / end actions mark / end',
'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2020 src is 2001::2 / udp src is 22 dst is 23 / end actions queue index 1 / mark / end']
self.create_fdir_rule(rule2[0:4], check_stats=False, msg="Rule already exists!: File exists", validate=False)
- self.create_fdir_rule(rule2[4:7], check_stats=False, msg="Invalid input action number: Invalid argument", validate=False)
+ self.create_fdir_rule(rule2[4:7], check_stats=False,
+ msg="error", validate=False)
self.create_fdir_rule(rule2[7:], check_stats=False, msg="Invalid input set: Invalid argument", validate=False)
self.check_fdir_rule(stats=True, rule_list=rule_li)
def test_conflicted_actions(self):
rule1 = "flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 1 / rss queues 2 3 end / end"
- self.create_fdir_rule(rule1, check_stats=False, msg="Invalid input action number: Invalid argument")
+ self.create_fdir_rule(rule1, check_stats=False, msg="error")
self.check_fdir_rule(stats=False)
def test_void_action(self):
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551
2020-10-15 9:48 [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551 sunqin
2020-10-15 5:14 ` Peng, Yuan
@ 2020-10-15 7:04 ` Sun, QinX
2020-10-16 6:56 ` Ma, LihongX
2 siblings, 0 replies; 4+ messages in thread
From: Sun, QinX @ 2020-10-15 7:04 UTC (permalink / raw)
To: Sun, QinX, dts
[-- Attachment #1: Type: text/plain, Size: 556 bytes --]
Tested-by: Sun, QinX<qinx.sun@intel.com>
Best Regards
Sun qin
> -----Original Message-----
> From: sunqin <qinx.sun@intel.com>
> Sent: Thursday, October 15, 2020 5:49 PM
> To: dts@dpdk.org
> Cc: Sun, QinX <qinx.sun@intel.com>
> Subject: [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log
> validation for wrong action according to the change of dpdk,dpdk commit
> id:cb97e595d9d3b316690c8d5ac688240d2ba1e551
>
> According to dpdk commit cb97e595d9d3b316690c8d5ac688240d2ba1e551 to
> modify log validation for wrong action
[-- Attachment #2: TestCVLFdir.log --]
[-- Type: application/octet-stream, Size: 151376 bytes --]
15/10/2020 15:13:26 dts:
TEST SUITE : TestCVLFdir
15/10/2020 15:13:26 dts: NIC : columbiaville_25g
15/10/2020 15:13:26 dut.10.240.183.254:
15/10/2020 15:13:26 tester:
15/10/2020 15:13:26 dut.10.240.183.254: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2,3,4 -n 4 -w 0000:03:00.0 -w 0000:03:00.1 --file-prefix=dpdk_22756_20201015151300 --log-level=ice,7 -- -i --portmask=0x3 --rxq=64 --txq=64 --port-topology=loop
15/10/2020 15:13:27 dut.10.240.183.254: EAL: Detected 72 lcore(s)
EAL: Detected 2 NUMA nodes
EAL: Multi-process socket /var/run/dpdk/dpdk_22756_20201015151300/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: No available hugepages reported in hugepages-1048576kB
EAL: Probing VFIO support...
EAL: VFIO support initialized
EAL: using IOMMU type 1 (Type 1)
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.0 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.1 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: No legacy callbacks, legacy socket not created
Interactive-mode selected
testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=171456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
Configuring Port 0 (socket 0)
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
Port 0: 68:05:CA:C1:B9:08
Configuring Port 1 (socket 0)
ice_interrupt_handler(): OICR: link state change event
Port 0: link state change event
ice_interrupt_handler(): OICR: link state change event
Port 0: link state change event
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:13:37 dut.10.240.183.254: port stop all
15/10/2020 15:13:38 dut.10.240.183.254:
Stopping ports...
ice_interrupt_handler(): OICR: link state change event
Port 0: link state change event
Checking link statuses...
ice_interrupt_handler(): OICR: link state change event
Port 1: link state change event
Done
15/10/2020 15:13:38 dut.10.240.183.254: port start all
15/10/2020 15:13:38 dut.10.240.183.254:
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 0: 68:05:CA:C1:B9:08
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:13:43 dut.10.240.183.254: set fwd rxonly
15/10/2020 15:13:43 dut.10.240.183.254:
Set rxonly packet forwarding mode
15/10/2020 15:13:43 dut.10.240.183.254: set verbose 1
15/10/2020 15:13:43 dut.10.240.183.254:
Change verbose level from 0 to 1
15/10/2020 15:13:43 dut.10.240.183.254: port config 0 udp_tunnel_port add vxlan 4789
15/10/2020 15:13:43 dut.10.240.183.254:
15/10/2020 15:13:43 dut.10.240.183.254: port config 1 udp_tunnel_port add vxlan 4789
15/10/2020 15:13:43 dut.10.240.183.254:
15/10/2020 15:13:43 dut.10.240.183.254: port config all rss all
15/10/2020 15:13:44 dut.10.240.183.254:
Port 0 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
Port 1 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
rss_hf 0x7f83fffc
15/10/2020 15:13:44 dut.10.240.183.254: port config 0 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:13:44 dut.10.240.183.254:
15/10/2020 15:13:44 dut.10.240.183.254: port config 1 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:13:44 dut.10.240.183.254:
15/10/2020 15:13:44 dut.10.240.183.254: show port info all
15/10/2020 15:13:44 dut.10.240.183.254:
********************* Infos for port 0 *********************
MAC address: 68:05:CA:C1:B9:08
Device name: 0000:03:00.0
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 64
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 64
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
********************* Infos for port 1 *********************
MAC address: 68:05:CA:C1:B9:09
Device name: 0000:03:00.1
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 64
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 64
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
15/10/2020 15:13:44 TestCVLFdir: Test Case test_conflicted_actions Begin
15/10/2020 15:13:44 dut.10.240.183.254:
15/10/2020 15:13:44 tester:
15/10/2020 15:13:44 dut.10.240.183.254: start
15/10/2020 15:13:44 dut.10.240.183.254:
rxonly packet forwarding - ports=2 - cores=1 - streams=128 - NUMA support enabled, MP allocation mode: native
Logical Core 2 (socket 0) forwards packets on 128 streams:
RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=1 (socket 0) -> TX P=0/Q=1 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=1 (socket 0) -> TX P=1/Q=1 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=2 (socket 0) -> TX P=0/Q=2 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=2 (socket 0) -> TX P=1/Q=2 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=3 (socket 0) -> TX P=0/Q=3 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=3 (socket 0) -> TX P=1/Q=3 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=4 (socket 0) -> TX P=0/Q=4 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=4 (socket 0) -> TX P=1/Q=4 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=5 (socket 0) -> TX P=0/Q=5 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=5 (socket 0) -> TX P=1/Q=5 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=6 (socket 0) -> TX P=0/Q=6 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=6 (socket 0) -> TX P=1/Q=6 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=7 (socket 0) -> TX P=0/Q=7 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=7 (socket 0) -> TX P=1/Q=7 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=8 (socket 0) -> TX P=0/Q=8 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=8 (socket 0) -> TX P=1/Q=8 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=9 (socket 0) -> TX P=0/Q=9 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=9 (socket 0) -> TX P=1/Q=9 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=10 (socket 0) -> TX P=0/Q=10 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=10 (socket 0) -> TX P=1/Q=10 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=11 (socket 0) -> TX P=0/Q=11 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=11 (socket 0) -> TX P=1/Q=11 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=12 (socket 0) -> TX P=0/Q=12 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=12 (socket 0) -> TX P=1/Q=12 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=13 (socket 0) -> TX P=0/Q=13 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=13 (socket 0) -> TX P=1/Q=13 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=14 (socket 0) -> TX P=0/Q=14 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=14 (socket 0) -> TX P=1/Q=14 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=15 (socket 0) -> TX P=0/Q=15 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=15 (socket 0) -> TX P=1/Q=15 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=16 (socket 0) -> TX P=0/Q=16 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=16 (socket 0) -> TX P=1/Q=16 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=17 (socket 0) -> TX P=0/Q=17 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=17 (socket 0) -> TX P=1/Q=17 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=18 (socket 0) -> TX P=0/Q=18 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=18 (socket 0) -> TX P=1/Q=18 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=19 (socket 0) -> TX P=0/Q=19 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=19 (socket 0) -> TX P=1/Q=19 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=20 (socket 0) -> TX P=0/Q=20 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=20 (socket 0) -> TX P=1/Q=20 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=21 (socket 0) -> TX P=0/Q=21 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=21 (socket 0) -> TX P=1/Q=21 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=22 (socket 0) -> TX P=0/Q=22 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=22 (socket 0) -> TX P=1/Q=22 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=23 (socket 0) -> TX P=0/Q=23 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=23 (socket 0) -> TX P=1/Q=23 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=24 (socket 0) -> TX P=0/Q=24 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=24 (socket 0) -> TX P=1/Q=24 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=25 (socket 0) -> TX P=0/Q=25 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=25 (socket 0) -> TX P=1/Q=25 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=26 (socket 0) -> TX P=0/Q=26 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=26 (socket 0) -> TX P=1/Q=26 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=27 (socket 0) -> TX P=0/Q=27 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=27 (socket 0) -> TX P=1/Q=27 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=28 (socket 0) -> TX P=0/Q=28 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=28 (socket 0) -> TX P=1/Q=28 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=29 (socket 0) -> TX P=0/Q=29 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=29 (socket 0) -> TX P=1/Q=29 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=30 (socket 0) -> TX P=0/Q=30 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=30 (socket 0) -> TX P=1/Q=30 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=31 (socket 0) -> TX P=0/Q=31 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=31 (socket 0) -> TX P=1/Q=31 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=32 (socket 0) -> TX P=0/Q=32 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=32 (socket 0) -> TX P=1/Q=32 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=33 (socket 0) -> TX P=0/Q=33 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=33 (socket 0) -> TX P=1/Q=33 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=34 (socket 0) -> TX P=0/Q=34 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=34 (socket 0) -> TX P=1/Q=34 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=35 (socket 0) -> TX P=0/Q=35 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=35 (socket 0) -> TX P=1/Q=35 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=36 (socket 0) -> TX P=0/Q=36 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=36 (socket 0) -> TX P=1/Q=36 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=37 (socket 0) -> TX P=0/Q=37 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=37 (socket 0) -> TX P=1/Q=37 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=38 (socket 0) -> TX P=0/Q=38 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=38 (socket 0) -> TX P=1/Q=38 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=39 (socket 0) -> TX P=0/Q=39 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=39 (socket 0) -> TX P=1/Q=39 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=40 (socket 0) -> TX P=0/Q=40 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=40 (socket 0) -> TX P=1/Q=40 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=41 (socket 0) -> TX P=0/Q=41 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=41 (socket 0) -> TX P=1/Q=41 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=42 (socket 0) -> TX P=0/Q=42 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=42 (socket 0) -> TX P=1/Q=42 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=43 (socket 0) -> TX P=0/Q=43 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=43 (socket 0) -> TX P=1/Q=43 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=44 (socket 0) -> TX P=0/Q=44 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=44 (socket 0) -> TX P=1/Q=44 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=45 (socket 0) -> TX P=0/Q=45 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=45 (socket 0) -> TX P=1/Q=45 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=46 (socket 0) -> TX P=0/Q=46 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=46 (socket 0) -> TX P=1/Q=46 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=47 (socket 0) -> TX P=0/Q=47 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=47 (socket 0) -> TX P=1/Q=47 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=48 (socket 0) -> TX P=0/Q=48 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=48 (socket 0) -> TX P=1/Q=48 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=49 (socket 0) -> TX P=0/Q=49 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=49 (socket 0) -> TX P=1/Q=49 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=50 (socket 0) -> TX P=0/Q=50 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=50 (socket 0) -> TX P=1/Q=50 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=51 (socket 0) -> TX P=0/Q=51 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=51 (socket 0) -> TX P=1/Q=51 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=52 (socket 0) -> TX P=0/Q=52 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=52 (socket 0) -> TX P=1/Q=52 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=53 (socket 0) -> TX P=0/Q=53 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=53 (socket 0) -> TX P=1/Q=53 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=54 (socket 0) -> TX P=0/Q=54 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=54 (socket 0) -> TX P=1/Q=54 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=55 (socket 0) -> TX P=0/Q=55 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=55 (socket 0) -> TX P=1/Q=55 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=56 (socket 0) -> TX P=0/Q=56 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=56 (socket 0) -> TX P=1/Q=56 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=57 (socket 0) -> TX P=0/Q=57 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=57 (socket 0) -> TX P=1/Q=57 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=58 (socket 0) -> TX P=0/Q=58 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=58 (socket 0) -> TX P=1/Q=58 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=59 (socket 0) -> TX P=0/Q=59 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=59 (socket 0) -> TX P=1/Q=59 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=60 (socket 0) -> TX P=0/Q=60 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=60 (socket 0) -> TX P=1/Q=60 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=61 (socket 0) -> TX P=0/Q=61 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=61 (socket 0) -> TX P=1/Q=61 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=62 (socket 0) -> TX P=0/Q=62 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=62 (socket 0) -> TX P=1/Q=62 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=63 (socket 0) -> TX P=0/Q=63 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=63 (socket 0) -> TX P=1/Q=63 (socket 0) peer=02:00:00:00:00:01
rxonly packet forwarding packets/burst=32
nb forwarding cores=1 - nb forwarding ports=2
port 0: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
port 1: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
15/10/2020 15:13:44 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 1 / rss queues 2 3 end / end
15/10/2020 15:13:44 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action number: Invalid argument
15/10/2020 15:13:44 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 1 / rss queues 2 3 end / end
15/10/2020 15:13:44 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action number: Invalid argument
15/10/2020 15:13:44 dut.10.240.183.254: flow list 0
15/10/2020 15:13:44 dut.10.240.183.254:
15/10/2020 15:13:44 TestCVLFdir: Test Case test_conflicted_actions Result PASSED:
15/10/2020 15:13:44 dut.10.240.183.254: flow flush 0
15/10/2020 15:13:45 dut.10.240.183.254:
testpmd>
15/10/2020 15:13:45 dut.10.240.183.254: flow flush 1
15/10/2020 15:13:47 dut.10.240.183.254:
testpmd>
15/10/2020 15:13:47 dut.10.240.183.254: clear port stats all
15/10/2020 15:13:48 dut.10.240.183.254:
NIC statistics for port 0 cleared
NIC statistics for port 1 cleared
testpmd>
15/10/2020 15:13:48 dut.10.240.183.254: stop
15/10/2020 15:13:48 dut.10.240.183.254:
Telling cores to ...
Waiting for lcores to finish...
---------------------- Forward statistics for port 0 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
---------------------- Forward statistics for port 1 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
+++++++++++++++ Accumulated forward statistics for all ports+++++++++++++++
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Done.
15/10/2020 15:13:48 TestCVLFdir: Test Case test_conflicted_rules Begin
15/10/2020 15:13:48 dut.10.240.183.254:
15/10/2020 15:13:48 tester:
15/10/2020 15:13:48 dut.10.240.183.254: start
15/10/2020 15:13:48 dut.10.240.183.254:
rxonly packet forwarding - ports=2 - cores=1 - streams=128 - NUMA support enabled, MP allocation mode: native
Logical Core 2 (socket 0) forwards packets on 128 streams:
RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=1 (socket 0) -> TX P=0/Q=1 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=1 (socket 0) -> TX P=1/Q=1 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=2 (socket 0) -> TX P=0/Q=2 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=2 (socket 0) -> TX P=1/Q=2 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=3 (socket 0) -> TX P=0/Q=3 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=3 (socket 0) -> TX P=1/Q=3 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=4 (socket 0) -> TX P=0/Q=4 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=4 (socket 0) -> TX P=1/Q=4 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=5 (socket 0) -> TX P=0/Q=5 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=5 (socket 0) -> TX P=1/Q=5 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=6 (socket 0) -> TX P=0/Q=6 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=6 (socket 0) -> TX P=1/Q=6 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=7 (socket 0) -> TX P=0/Q=7 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=7 (socket 0) -> TX P=1/Q=7 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=8 (socket 0) -> TX P=0/Q=8 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=8 (socket 0) -> TX P=1/Q=8 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=9 (socket 0) -> TX P=0/Q=9 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=9 (socket 0) -> TX P=1/Q=9 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=10 (socket 0) -> TX P=0/Q=10 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=10 (socket 0) -> TX P=1/Q=10 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=11 (socket 0) -> TX P=0/Q=11 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=11 (socket 0) -> TX P=1/Q=11 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=12 (socket 0) -> TX P=0/Q=12 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=12 (socket 0) -> TX P=1/Q=12 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=13 (socket 0) -> TX P=0/Q=13 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=13 (socket 0) -> TX P=1/Q=13 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=14 (socket 0) -> TX P=0/Q=14 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=14 (socket 0) -> TX P=1/Q=14 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=15 (socket 0) -> TX P=0/Q=15 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=15 (socket 0) -> TX P=1/Q=15 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=16 (socket 0) -> TX P=0/Q=16 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=16 (socket 0) -> TX P=1/Q=16 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=17 (socket 0) -> TX P=0/Q=17 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=17 (socket 0) -> TX P=1/Q=17 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=18 (socket 0) -> TX P=0/Q=18 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=18 (socket 0) -> TX P=1/Q=18 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=19 (socket 0) -> TX P=0/Q=19 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=19 (socket 0) -> TX P=1/Q=19 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=20 (socket 0) -> TX P=0/Q=20 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=20 (socket 0) -> TX P=1/Q=20 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=21 (socket 0) -> TX P=0/Q=21 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=21 (socket 0) -> TX P=1/Q=21 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=22 (socket 0) -> TX P=0/Q=22 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=22 (socket 0) -> TX P=1/Q=22 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=23 (socket 0) -> TX P=0/Q=23 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=23 (socket 0) -> TX P=1/Q=23 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=24 (socket 0) -> TX P=0/Q=24 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=24 (socket 0) -> TX P=1/Q=24 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=25 (socket 0) -> TX P=0/Q=25 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=25 (socket 0) -> TX P=1/Q=25 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=26 (socket 0) -> TX P=0/Q=26 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=26 (socket 0) -> TX P=1/Q=26 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=27 (socket 0) -> TX P=0/Q=27 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=27 (socket 0) -> TX P=1/Q=27 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=28 (socket 0) -> TX P=0/Q=28 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=28 (socket 0) -> TX P=1/Q=28 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=29 (socket 0) -> TX P=0/Q=29 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=29 (socket 0) -> TX P=1/Q=29 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=30 (socket 0) -> TX P=0/Q=30 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=30 (socket 0) -> TX P=1/Q=30 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=31 (socket 0) -> TX P=0/Q=31 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=31 (socket 0) -> TX P=1/Q=31 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=32 (socket 0) -> TX P=0/Q=32 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=32 (socket 0) -> TX P=1/Q=32 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=33 (socket 0) -> TX P=0/Q=33 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=33 (socket 0) -> TX P=1/Q=33 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=34 (socket 0) -> TX P=0/Q=34 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=34 (socket 0) -> TX P=1/Q=34 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=35 (socket 0) -> TX P=0/Q=35 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=35 (socket 0) -> TX P=1/Q=35 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=36 (socket 0) -> TX P=0/Q=36 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=36 (socket 0) -> TX P=1/Q=36 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=37 (socket 0) -> TX P=0/Q=37 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=37 (socket 0) -> TX P=1/Q=37 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=38 (socket 0) -> TX P=0/Q=38 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=38 (socket 0) -> TX P=1/Q=38 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=39 (socket 0) -> TX P=0/Q=39 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=39 (socket 0) -> TX P=1/Q=39 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=40 (socket 0) -> TX P=0/Q=40 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=40 (socket 0) -> TX P=1/Q=40 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=41 (socket 0) -> TX P=0/Q=41 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=41 (socket 0) -> TX P=1/Q=41 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=42 (socket 0) -> TX P=0/Q=42 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=42 (socket 0) -> TX P=1/Q=42 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=43 (socket 0) -> TX P=0/Q=43 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=43 (socket 0) -> TX P=1/Q=43 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=44 (socket 0) -> TX P=0/Q=44 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=44 (socket 0) -> TX P=1/Q=44 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=45 (socket 0) -> TX P=0/Q=45 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=45 (socket 0) -> TX P=1/Q=45 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=46 (socket 0) -> TX P=0/Q=46 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=46 (socket 0) -> TX P=1/Q=46 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=47 (socket 0) -> TX P=0/Q=47 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=47 (socket 0) -> TX P=1/Q=47 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=48 (socket 0) -> TX P=0/Q=48 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=48 (socket 0) -> TX P=1/Q=48 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=49 (socket 0) -> TX P=0/Q=49 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=49 (socket 0) -> TX P=1/Q=49 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=50 (socket 0) -> TX P=0/Q=50 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=50 (socket 0) -> TX P=1/Q=50 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=51 (socket 0) -> TX P=0/Q=51 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=51 (socket 0) -> TX P=1/Q=51 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=52 (socket 0) -> TX P=0/Q=52 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=52 (socket 0) -> TX P=1/Q=52 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=53 (socket 0) -> TX P=0/Q=53 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=53 (socket 0) -> TX P=1/Q=53 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=54 (socket 0) -> TX P=0/Q=54 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=54 (socket 0) -> TX P=1/Q=54 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=55 (socket 0) -> TX P=0/Q=55 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=55 (socket 0) -> TX P=1/Q=55 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=56 (socket 0) -> TX P=0/Q=56 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=56 (socket 0) -> TX P=1/Q=56 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=57 (socket 0) -> TX P=0/Q=57 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=57 (socket 0) -> TX P=1/Q=57 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=58 (socket 0) -> TX P=0/Q=58 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=58 (socket 0) -> TX P=1/Q=58 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=59 (socket 0) -> TX P=0/Q=59 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=59 (socket 0) -> TX P=1/Q=59 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=60 (socket 0) -> TX P=0/Q=60 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=60 (socket 0) -> TX P=1/Q=60 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=61 (socket 0) -> TX P=0/Q=61 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=61 (socket 0) -> TX P=1/Q=61 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=62 (socket 0) -> TX P=0/Q=62 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=62 (socket 0) -> TX P=1/Q=62 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=63 (socket 0) -> TX P=0/Q=63 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=63 (socket 0) -> TX P=1/Q=63 (socket 0) peer=02:00:00:00:00:01
rxonly packet forwarding packets/burst=32
nb forwarding cores=1 - nb forwarding ports=2
port 0: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
port 1: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
15/10/2020 15:13:48 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 1 / end
15/10/2020 15:13:48 dut.10.240.183.254:
Flow rule validated
15/10/2020 15:13:48 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2020 src is 2001::2 / end actions queue index 1 / mark / end
15/10/2020 15:13:48 dut.10.240.183.254:
Flow rule validated
15/10/2020 15:13:48 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 1 / end
15/10/2020 15:13:48 dut.10.240.183.254:
ice_flow_create(): Succeeded to create (1) flow
Flow rule #0 created
15/10/2020 15:13:48 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2020 src is 2001::2 / end actions queue index 1 / mark / end
15/10/2020 15:13:48 dut.10.240.183.254:
ice_flow_create(): Succeeded to create (1) flow
Flow rule #1 created
15/10/2020 15:13:48 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 2 / end
15/10/2020 15:13:48 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 2 (flow rule (handle)): Rule already exists!: File exists
15/10/2020 15:13:48 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions drop / end
15/10/2020 15:13:48 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 2 (flow rule (handle)): Rule already exists!: File exists
15/10/2020 15:13:48 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2020 src is 2001::2 / end actions queue index 2 / mark / end
15/10/2020 15:13:49 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 2 (flow rule (handle)): Rule already exists!: File exists
15/10/2020 15:13:49 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2020 src is 2001::2 / end actions rss queues 2 3 end / mark / end
15/10/2020 15:13:49 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 2 (flow rule (handle)): Rule already exists!: File exists
15/10/2020 15:13:49 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 3 / mark / end
15/10/2020 15:13:49 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type: Invalid argument
15/10/2020 15:13:49 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / udp src is 22 dst is 23 / end actions queue index 3 / mark / end
15/10/2020 15:13:49 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4078, Invalid action type: Invalid argument
15/10/2020 15:13:49 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2021 / end actions mark / end
15/10/2020 15:13:49 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type: Invalid argument
15/10/2020 15:13:49 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2020 src is 2001::2 / udp src is 22 dst is 23 / end actions queue index 1 / mark / end
15/10/2020 15:13:49 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 10 (item specification): cause: 0x7ffd402b3ff8, Invalid input set: Invalid argument
15/10/2020 15:13:49 dut.10.240.183.254: flow list 0
15/10/2020 15:13:49 dut.10.240.183.254:
ID Group Prio Attr Rule
0 0 0 i-- ETH IPV4 => QUEUE
1 0 0 i-- ETH IPV6 => QUEUE MARK
15/10/2020 15:13:49 TestCVLFdir: Test Case test_conflicted_rules Result PASSED:
15/10/2020 15:13:49 dut.10.240.183.254: flow flush 0
15/10/2020 15:13:50 dut.10.240.183.254:
testpmd>
15/10/2020 15:13:50 dut.10.240.183.254: flow flush 1
15/10/2020 15:13:51 dut.10.240.183.254:
testpmd>
15/10/2020 15:13:51 dut.10.240.183.254: clear port stats all
15/10/2020 15:13:52 dut.10.240.183.254:
NIC statistics for port 0 cleared
NIC statistics for port 1 cleared
testpmd>
15/10/2020 15:13:52 dut.10.240.183.254: stop
15/10/2020 15:13:52 dut.10.240.183.254:
Telling cores to ...
Waiting for lcores to finish...
---------------------- Forward statistics for port 0 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
---------------------- Forward statistics for port 1 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
+++++++++++++++ Accumulated forward statistics for all ports+++++++++++++++
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Done.
15/10/2020 15:13:52 TestCVLFdir: Test Case test_invalid_parameters_of_queue_index Begin
15/10/2020 15:13:53 dut.10.240.183.254:
15/10/2020 15:13:53 tester:
15/10/2020 15:13:53 dut.10.240.183.254: start
15/10/2020 15:13:53 dut.10.240.183.254:
rxonly packet forwarding - ports=2 - cores=1 - streams=128 - NUMA support enabled, MP allocation mode: native
Logical Core 2 (socket 0) forwards packets on 128 streams:
RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=1 (socket 0) -> TX P=0/Q=1 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=1 (socket 0) -> TX P=1/Q=1 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=2 (socket 0) -> TX P=0/Q=2 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=2 (socket 0) -> TX P=1/Q=2 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=3 (socket 0) -> TX P=0/Q=3 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=3 (socket 0) -> TX P=1/Q=3 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=4 (socket 0) -> TX P=0/Q=4 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=4 (socket 0) -> TX P=1/Q=4 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=5 (socket 0) -> TX P=0/Q=5 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=5 (socket 0) -> TX P=1/Q=5 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=6 (socket 0) -> TX P=0/Q=6 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=6 (socket 0) -> TX P=1/Q=6 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=7 (socket 0) -> TX P=0/Q=7 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=7 (socket 0) -> TX P=1/Q=7 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=8 (socket 0) -> TX P=0/Q=8 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=8 (socket 0) -> TX P=1/Q=8 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=9 (socket 0) -> TX P=0/Q=9 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=9 (socket 0) -> TX P=1/Q=9 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=10 (socket 0) -> TX P=0/Q=10 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=10 (socket 0) -> TX P=1/Q=10 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=11 (socket 0) -> TX P=0/Q=11 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=11 (socket 0) -> TX P=1/Q=11 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=12 (socket 0) -> TX P=0/Q=12 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=12 (socket 0) -> TX P=1/Q=12 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=13 (socket 0) -> TX P=0/Q=13 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=13 (socket 0) -> TX P=1/Q=13 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=14 (socket 0) -> TX P=0/Q=14 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=14 (socket 0) -> TX P=1/Q=14 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=15 (socket 0) -> TX P=0/Q=15 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=15 (socket 0) -> TX P=1/Q=15 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=16 (socket 0) -> TX P=0/Q=16 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=16 (socket 0) -> TX P=1/Q=16 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=17 (socket 0) -> TX P=0/Q=17 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=17 (socket 0) -> TX P=1/Q=17 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=18 (socket 0) -> TX P=0/Q=18 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=18 (socket 0) -> TX P=1/Q=18 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=19 (socket 0) -> TX P=0/Q=19 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=19 (socket 0) -> TX P=1/Q=19 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=20 (socket 0) -> TX P=0/Q=20 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=20 (socket 0) -> TX P=1/Q=20 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=21 (socket 0) -> TX P=0/Q=21 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=21 (socket 0) -> TX P=1/Q=21 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=22 (socket 0) -> TX P=0/Q=22 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=22 (socket 0) -> TX P=1/Q=22 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=23 (socket 0) -> TX P=0/Q=23 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=23 (socket 0) -> TX P=1/Q=23 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=24 (socket 0) -> TX P=0/Q=24 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=24 (socket 0) -> TX P=1/Q=24 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=25 (socket 0) -> TX P=0/Q=25 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=25 (socket 0) -> TX P=1/Q=25 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=26 (socket 0) -> TX P=0/Q=26 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=26 (socket 0) -> TX P=1/Q=26 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=27 (socket 0) -> TX P=0/Q=27 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=27 (socket 0) -> TX P=1/Q=27 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=28 (socket 0) -> TX P=0/Q=28 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=28 (socket 0) -> TX P=1/Q=28 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=29 (socket 0) -> TX P=0/Q=29 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=29 (socket 0) -> TX P=1/Q=29 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=30 (socket 0) -> TX P=0/Q=30 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=30 (socket 0) -> TX P=1/Q=30 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=31 (socket 0) -> TX P=0/Q=31 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=31 (socket 0) -> TX P=1/Q=31 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=32 (socket 0) -> TX P=0/Q=32 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=32 (socket 0) -> TX P=1/Q=32 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=33 (socket 0) -> TX P=0/Q=33 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=33 (socket 0) -> TX P=1/Q=33 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=34 (socket 0) -> TX P=0/Q=34 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=34 (socket 0) -> TX P=1/Q=34 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=35 (socket 0) -> TX P=0/Q=35 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=35 (socket 0) -> TX P=1/Q=35 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=36 (socket 0) -> TX P=0/Q=36 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=36 (socket 0) -> TX P=1/Q=36 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=37 (socket 0) -> TX P=0/Q=37 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=37 (socket 0) -> TX P=1/Q=37 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=38 (socket 0) -> TX P=0/Q=38 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=38 (socket 0) -> TX P=1/Q=38 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=39 (socket 0) -> TX P=0/Q=39 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=39 (socket 0) -> TX P=1/Q=39 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=40 (socket 0) -> TX P=0/Q=40 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=40 (socket 0) -> TX P=1/Q=40 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=41 (socket 0) -> TX P=0/Q=41 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=41 (socket 0) -> TX P=1/Q=41 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=42 (socket 0) -> TX P=0/Q=42 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=42 (socket 0) -> TX P=1/Q=42 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=43 (socket 0) -> TX P=0/Q=43 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=43 (socket 0) -> TX P=1/Q=43 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=44 (socket 0) -> TX P=0/Q=44 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=44 (socket 0) -> TX P=1/Q=44 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=45 (socket 0) -> TX P=0/Q=45 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=45 (socket 0) -> TX P=1/Q=45 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=46 (socket 0) -> TX P=0/Q=46 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=46 (socket 0) -> TX P=1/Q=46 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=47 (socket 0) -> TX P=0/Q=47 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=47 (socket 0) -> TX P=1/Q=47 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=48 (socket 0) -> TX P=0/Q=48 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=48 (socket 0) -> TX P=1/Q=48 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=49 (socket 0) -> TX P=0/Q=49 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=49 (socket 0) -> TX P=1/Q=49 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=50 (socket 0) -> TX P=0/Q=50 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=50 (socket 0) -> TX P=1/Q=50 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=51 (socket 0) -> TX P=0/Q=51 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=51 (socket 0) -> TX P=1/Q=51 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=52 (socket 0) -> TX P=0/Q=52 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=52 (socket 0) -> TX P=1/Q=52 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=53 (socket 0) -> TX P=0/Q=53 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=53 (socket 0) -> TX P=1/Q=53 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=54 (socket 0) -> TX P=0/Q=54 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=54 (socket 0) -> TX P=1/Q=54 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=55 (socket 0) -> TX P=0/Q=55 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=55 (socket 0) -> TX P=1/Q=55 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=56 (socket 0) -> TX P=0/Q=56 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=56 (socket 0) -> TX P=1/Q=56 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=57 (socket 0) -> TX P=0/Q=57 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=57 (socket 0) -> TX P=1/Q=57 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=58 (socket 0) -> TX P=0/Q=58 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=58 (socket 0) -> TX P=1/Q=58 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=59 (socket 0) -> TX P=0/Q=59 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=59 (socket 0) -> TX P=1/Q=59 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=60 (socket 0) -> TX P=0/Q=60 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=60 (socket 0) -> TX P=1/Q=60 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=61 (socket 0) -> TX P=0/Q=61 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=61 (socket 0) -> TX P=1/Q=61 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=62 (socket 0) -> TX P=0/Q=62 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=62 (socket 0) -> TX P=1/Q=62 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=63 (socket 0) -> TX P=0/Q=63 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=63 (socket 0) -> TX P=1/Q=63 (socket 0) peer=02:00:00:00:00:01
rxonly packet forwarding packets/burst=32
nb forwarding cores=1 - nb forwarding ports=2
port 0: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
port 1: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
15/10/2020 15:13:53 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions queue index 64 / end
15/10/2020 15:13:54 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type or queue number: Invalid argument
testpmd>
15/10/2020 15:13:54 dut.10.240.183.254: flow list 0
15/10/2020 15:13:54 dut.10.240.183.254:
15/10/2020 15:13:54 TestCVLFdir: Test Case test_invalid_parameters_of_queue_index Result PASSED:
15/10/2020 15:13:54 dut.10.240.183.254: flow flush 0
15/10/2020 15:13:55 dut.10.240.183.254:
testpmd>
15/10/2020 15:13:55 dut.10.240.183.254: flow flush 1
15/10/2020 15:13:56 dut.10.240.183.254:
testpmd>
15/10/2020 15:13:56 dut.10.240.183.254: clear port stats all
15/10/2020 15:13:57 dut.10.240.183.254:
NIC statistics for port 0 cleared
NIC statistics for port 1 cleared
testpmd>
15/10/2020 15:13:57 dut.10.240.183.254: stop
15/10/2020 15:13:58 dut.10.240.183.254:
Telling cores to ...
Waiting for lcores to finish...
---------------------- Forward statistics for port 0 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
---------------------- Forward statistics for port 1 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
+++++++++++++++ Accumulated forward statistics for all ports+++++++++++++++
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Done.
15/10/2020 15:13:58 TestCVLFdir: Test Case test_invalid_parameters_of_rss_queues Begin
15/10/2020 15:13:58 dut.10.240.183.254:
15/10/2020 15:13:58 tester:
15/10/2020 15:13:58 dut.10.240.183.254: start
15/10/2020 15:13:58 dut.10.240.183.254:
rxonly packet forwarding - ports=2 - cores=1 - streams=128 - NUMA support enabled, MP allocation mode: native
Logical Core 2 (socket 0) forwards packets on 128 streams:
RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=1 (socket 0) -> TX P=0/Q=1 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=1 (socket 0) -> TX P=1/Q=1 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=2 (socket 0) -> TX P=0/Q=2 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=2 (socket 0) -> TX P=1/Q=2 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=3 (socket 0) -> TX P=0/Q=3 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=3 (socket 0) -> TX P=1/Q=3 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=4 (socket 0) -> TX P=0/Q=4 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=4 (socket 0) -> TX P=1/Q=4 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=5 (socket 0) -> TX P=0/Q=5 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=5 (socket 0) -> TX P=1/Q=5 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=6 (socket 0) -> TX P=0/Q=6 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=6 (socket 0) -> TX P=1/Q=6 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=7 (socket 0) -> TX P=0/Q=7 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=7 (socket 0) -> TX P=1/Q=7 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=8 (socket 0) -> TX P=0/Q=8 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=8 (socket 0) -> TX P=1/Q=8 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=9 (socket 0) -> TX P=0/Q=9 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=9 (socket 0) -> TX P=1/Q=9 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=10 (socket 0) -> TX P=0/Q=10 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=10 (socket 0) -> TX P=1/Q=10 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=11 (socket 0) -> TX P=0/Q=11 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=11 (socket 0) -> TX P=1/Q=11 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=12 (socket 0) -> TX P=0/Q=12 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=12 (socket 0) -> TX P=1/Q=12 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=13 (socket 0) -> TX P=0/Q=13 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=13 (socket 0) -> TX P=1/Q=13 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=14 (socket 0) -> TX P=0/Q=14 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=14 (socket 0) -> TX P=1/Q=14 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=15 (socket 0) -> TX P=0/Q=15 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=15 (socket 0) -> TX P=1/Q=15 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=16 (socket 0) -> TX P=0/Q=16 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=16 (socket 0) -> TX P=1/Q=16 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=17 (socket 0) -> TX P=0/Q=17 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=17 (socket 0) -> TX P=1/Q=17 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=18 (socket 0) -> TX P=0/Q=18 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=18 (socket 0) -> TX P=1/Q=18 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=19 (socket 0) -> TX P=0/Q=19 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=19 (socket 0) -> TX P=1/Q=19 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=20 (socket 0) -> TX P=0/Q=20 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=20 (socket 0) -> TX P=1/Q=20 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=21 (socket 0) -> TX P=0/Q=21 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=21 (socket 0) -> TX P=1/Q=21 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=22 (socket 0) -> TX P=0/Q=22 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=22 (socket 0) -> TX P=1/Q=22 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=23 (socket 0) -> TX P=0/Q=23 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=23 (socket 0) -> TX P=1/Q=23 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=24 (socket 0) -> TX P=0/Q=24 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=24 (socket 0) -> TX P=1/Q=24 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=25 (socket 0) -> TX P=0/Q=25 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=25 (socket 0) -> TX P=1/Q=25 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=26 (socket 0) -> TX P=0/Q=26 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=26 (socket 0) -> TX P=1/Q=26 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=27 (socket 0) -> TX P=0/Q=27 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=27 (socket 0) -> TX P=1/Q=27 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=28 (socket 0) -> TX P=0/Q=28 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=28 (socket 0) -> TX P=1/Q=28 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=29 (socket 0) -> TX P=0/Q=29 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=29 (socket 0) -> TX P=1/Q=29 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=30 (socket 0) -> TX P=0/Q=30 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=30 (socket 0) -> TX P=1/Q=30 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=31 (socket 0) -> TX P=0/Q=31 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=31 (socket 0) -> TX P=1/Q=31 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=32 (socket 0) -> TX P=0/Q=32 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=32 (socket 0) -> TX P=1/Q=32 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=33 (socket 0) -> TX P=0/Q=33 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=33 (socket 0) -> TX P=1/Q=33 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=34 (socket 0) -> TX P=0/Q=34 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=34 (socket 0) -> TX P=1/Q=34 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=35 (socket 0) -> TX P=0/Q=35 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=35 (socket 0) -> TX P=1/Q=35 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=36 (socket 0) -> TX P=0/Q=36 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=36 (socket 0) -> TX P=1/Q=36 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=37 (socket 0) -> TX P=0/Q=37 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=37 (socket 0) -> TX P=1/Q=37 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=38 (socket 0) -> TX P=0/Q=38 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=38 (socket 0) -> TX P=1/Q=38 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=39 (socket 0) -> TX P=0/Q=39 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=39 (socket 0) -> TX P=1/Q=39 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=40 (socket 0) -> TX P=0/Q=40 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=40 (socket 0) -> TX P=1/Q=40 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=41 (socket 0) -> TX P=0/Q=41 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=41 (socket 0) -> TX P=1/Q=41 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=42 (socket 0) -> TX P=0/Q=42 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=42 (socket 0) -> TX P=1/Q=42 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=43 (socket 0) -> TX P=0/Q=43 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=43 (socket 0) -> TX P=1/Q=43 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=44 (socket 0) -> TX P=0/Q=44 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=44 (socket 0) -> TX P=1/Q=44 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=45 (socket 0) -> TX P=0/Q=45 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=45 (socket 0) -> TX P=1/Q=45 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=46 (socket 0) -> TX P=0/Q=46 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=46 (socket 0) -> TX P=1/Q=46 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=47 (socket 0) -> TX P=0/Q=47 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=47 (socket 0) -> TX P=1/Q=47 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=48 (socket 0) -> TX P=0/Q=48 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=48 (socket 0) -> TX P=1/Q=48 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=49 (socket 0) -> TX P=0/Q=49 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=49 (socket 0) -> TX P=1/Q=49 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=50 (socket 0) -> TX P=0/Q=50 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=50 (socket 0) -> TX P=1/Q=50 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=51 (socket 0) -> TX P=0/Q=51 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=51 (socket 0) -> TX P=1/Q=51 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=52 (socket 0) -> TX P=0/Q=52 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=52 (socket 0) -> TX P=1/Q=52 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=53 (socket 0) -> TX P=0/Q=53 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=53 (socket 0) -> TX P=1/Q=53 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=54 (socket 0) -> TX P=0/Q=54 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=54 (socket 0) -> TX P=1/Q=54 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=55 (socket 0) -> TX P=0/Q=55 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=55 (socket 0) -> TX P=1/Q=55 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=56 (socket 0) -> TX P=0/Q=56 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=56 (socket 0) -> TX P=1/Q=56 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=57 (socket 0) -> TX P=0/Q=57 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=57 (socket 0) -> TX P=1/Q=57 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=58 (socket 0) -> TX P=0/Q=58 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=58 (socket 0) -> TX P=1/Q=58 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=59 (socket 0) -> TX P=0/Q=59 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=59 (socket 0) -> TX P=1/Q=59 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=60 (socket 0) -> TX P=0/Q=60 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=60 (socket 0) -> TX P=1/Q=60 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=61 (socket 0) -> TX P=0/Q=61 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=61 (socket 0) -> TX P=1/Q=61 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=62 (socket 0) -> TX P=0/Q=62 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=62 (socket 0) -> TX P=1/Q=62 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=63 (socket 0) -> TX P=0/Q=63 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=63 (socket 0) -> TX P=1/Q=63 (socket 0) peer=02:00:00:00:00:01
rxonly packet forwarding packets/burst=32
nb forwarding cores=1 - nb forwarding ports=2
port 0: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
port 1: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
15/10/2020 15:13:58 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type or queue number: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 0 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type or queue number: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues end / end
15/10/2020 15:13:58 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type or queue number: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type or queue number: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 0 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type or queue number: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues end / end
15/10/2020 15:13:58 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid action type or queue number: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 5 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Discontinuous queue region: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 5 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Discontinuous queue region: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 63 64 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid queue region indexes: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 63 64 end / end
15/10/2020 15:13:58 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffd402b4058, Invalid queue region indexes: Invalid argument
15/10/2020 15:13:58 dut.10.240.183.254: quit
15/10/2020 15:14:00 dut.10.240.183.254:
Telling cores to stop...
Waiting for lcores to finish...
---------------------- Forward statistics for port 0 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
---------------------- Forward statistics for port 1 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
+++++++++++++++ Accumulated forward statistics for all ports+++++++++++++++
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Done.
Stopping port 0...
Stopping ports...
Done
Stopping port 1...
Stopping ports...
ice_interrupt_handler(): OICR: link state change event
Port 0: link state change event
Done
Shutting down port 0...
Closing ports...
EAL: Error: Invalid memory
EAL: Error: Invalid memory
Port 0 is closed
Done
Shutting down port 1...
Closing ports...
Port 1 is closed
Done
Bye...
15/10/2020 15:14:00 dut.10.240.183.254: kill_all: called by dut and prefix list has value.
15/10/2020 15:14:00 dut.10.240.183.254: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2,3,4 -n 4 -w 0000:03:00.0 -w 0000:03:00.1 --file-prefix=dpdk_22756_20201015151300 --log-level=ice,7 -- -i --portmask=0x3 --rxq=7 --txq=7 --port-topology=loop
15/10/2020 15:14:02 dut.10.240.183.254: EAL: Detected 72 lcore(s)
EAL: Detected 2 NUMA nodes
EAL: Multi-process socket /var/run/dpdk/dpdk_22756_20201015151300/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: No available hugepages reported in hugepages-1048576kB
EAL: Probing VFIO support...
EAL: VFIO support initialized
EAL: using IOMMU type 1 (Type 1)
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.0 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.1 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: No legacy callbacks, legacy socket not created
Interactive-mode selected
testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=171456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
Configuring Port 0 (socket 0)
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
Port 0: 68:05:CA:C1:B9:08
Configuring Port 1 (socket 0)
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:14:12 dut.10.240.183.254: port stop all
15/10/2020 15:14:12 dut.10.240.183.254:
Stopping ports...
Checking link statuses...
Done
15/10/2020 15:14:12 dut.10.240.183.254: port start all
15/10/2020 15:14:12 dut.10.240.183.254:
ice_interrupt_handler(): OICR: link state change event
Port 0: link state change event
ice_interrupt_handler(): OICR: link state change event
Port 1: link state change event
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 0: 68:05:CA:C1:B9:08
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:14:17 dut.10.240.183.254: set fwd rxonly
15/10/2020 15:14:17 dut.10.240.183.254:
Set rxonly packet forwarding mode
15/10/2020 15:14:17 dut.10.240.183.254: set verbose 1
15/10/2020 15:14:17 dut.10.240.183.254:
Change verbose level from 0 to 1
15/10/2020 15:14:17 dut.10.240.183.254: port config 0 udp_tunnel_port add vxlan 4789
15/10/2020 15:14:17 dut.10.240.183.254:
15/10/2020 15:14:17 dut.10.240.183.254: port config 1 udp_tunnel_port add vxlan 4789
15/10/2020 15:14:17 dut.10.240.183.254:
15/10/2020 15:14:17 dut.10.240.183.254: port config all rss all
15/10/2020 15:14:17 dut.10.240.183.254:
Port 0 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
Port 1 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
rss_hf 0x7f83fffc
15/10/2020 15:14:17 dut.10.240.183.254: port config 0 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:14:17 dut.10.240.183.254:
15/10/2020 15:14:17 dut.10.240.183.254: port config 1 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:14:17 dut.10.240.183.254:
15/10/2020 15:14:17 dut.10.240.183.254: show port info all
15/10/2020 15:14:18 dut.10.240.183.254:
********************* Infos for port 0 *********************
MAC address: 68:05:CA:C1:B9:08
Device name: 0000:03:00.0
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 7
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 7
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
********************* Infos for port 1 *********************
MAC address: 68:05:CA:C1:B9:09
Device name: 0000:03:00.1
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 7
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 7
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
15/10/2020 15:14:18 dut.10.240.183.254: start
15/10/2020 15:14:18 dut.10.240.183.254:
rxonly packet forwarding - ports=2 - cores=1 - streams=14 - NUMA support enabled, MP allocation mode: native
Logical Core 2 (socket 0) forwards packets on 14 streams:
RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=1 (socket 0) -> TX P=0/Q=1 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=1 (socket 0) -> TX P=1/Q=1 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=2 (socket 0) -> TX P=0/Q=2 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=2 (socket 0) -> TX P=1/Q=2 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=3 (socket 0) -> TX P=0/Q=3 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=3 (socket 0) -> TX P=1/Q=3 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=4 (socket 0) -> TX P=0/Q=4 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=4 (socket 0) -> TX P=1/Q=4 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=5 (socket 0) -> TX P=0/Q=5 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=5 (socket 0) -> TX P=1/Q=5 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=6 (socket 0) -> TX P=0/Q=6 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=6 (socket 0) -> TX P=1/Q=6 (socket 0) peer=02:00:00:00:00:01
rxonly packet forwarding packets/burst=32
nb forwarding cores=1 - nb forwarding ports=2
port 0: RX queue number: 7 Tx queue number: 7
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
port 1: RX queue number: 7 Tx queue number: 7
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
15/10/2020 15:14:18 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 proto is 255 / end actions rss queues 0 1 2 3 4 5 6 7 end / end
15/10/2020 15:14:18 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffe4885b818, Invalid queue region indexes: Invalid argument
15/10/2020 15:14:18 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 proto is 255 / end actions rss queues 0 1 2 3 4 5 6 7 end / end
15/10/2020 15:14:18 dut.10.240.183.254:
ice_flow_create(): Failed to create flow
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffe4885b818, Invalid queue region indexes: Invalid argument
15/10/2020 15:14:18 dut.10.240.183.254: flow list 0
15/10/2020 15:14:18 dut.10.240.183.254:
15/10/2020 15:14:18 dut.10.240.183.254: quit
15/10/2020 15:14:19 dut.10.240.183.254:
Telling cores to stop...
Waiting for lcores to finish...
---------------------- Forward statistics for port 0 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
---------------------- Forward statistics for port 1 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
+++++++++++++++ Accumulated forward statistics for all ports+++++++++++++++
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Done.
Stopping port 0...
Stopping ports...
Done
Stopping port 1...
Stopping ports...
Done
Shutting down port 0...
Closing ports...
Port 0 is closed
Done
Shutting down port 1...
Closing ports...
Port 1 is closed
Done
Bye...
15/10/2020 15:14:19 dut.10.240.183.254: kill_all: called by dut and prefix list has value.
15/10/2020 15:14:19 dut.10.240.183.254: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2,3,4 -n 4 -w 0000:03:00.0 -w 0000:03:00.1 --file-prefix=dpdk_22756_20201015151300 --log-level=ice,7 -- -i --portmask=0x3 --rxq=8 --txq=8 --port-topology=loop
15/10/2020 15:14:21 dut.10.240.183.254: EAL: Detected 72 lcore(s)
EAL: Detected 2 NUMA nodes
EAL: Multi-process socket /var/run/dpdk/dpdk_22756_20201015151300/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: No available hugepages reported in hugepages-1048576kB
EAL: Probing VFIO support...
EAL: VFIO support initialized
EAL: using IOMMU type 1 (Type 1)
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.0 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.1 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: No legacy callbacks, legacy socket not created
Interactive-mode selected
testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=171456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
Configuring Port 0 (socket 0)
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
Port 0: 68:05:CA:C1:B9:08
Configuring Port 1 (socket 0)
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:14:31 dut.10.240.183.254: port stop all
15/10/2020 15:14:31 dut.10.240.183.254:
Stopping ports...
Checking link statuses...
Done
15/10/2020 15:14:31 dut.10.240.183.254: port start all
15/10/2020 15:14:31 dut.10.240.183.254:
ice_interrupt_handler(): OICR: link state change event
Port 0: link state change event
ice_interrupt_handler(): OICR: link state change event
Port 1: link state change event
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 0: 68:05:CA:C1:B9:08
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:14:36 dut.10.240.183.254: set fwd rxonly
15/10/2020 15:14:36 dut.10.240.183.254:
Set rxonly packet forwarding mode
15/10/2020 15:14:36 dut.10.240.183.254: set verbose 1
15/10/2020 15:14:36 dut.10.240.183.254:
Change verbose level from 0 to 1
15/10/2020 15:14:36 dut.10.240.183.254: port config 0 udp_tunnel_port add vxlan 4789
15/10/2020 15:14:36 dut.10.240.183.254:
15/10/2020 15:14:36 dut.10.240.183.254: port config 1 udp_tunnel_port add vxlan 4789
15/10/2020 15:14:36 dut.10.240.183.254:
15/10/2020 15:14:36 dut.10.240.183.254: port config all rss all
15/10/2020 15:14:36 dut.10.240.183.254:
Port 0 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
Port 1 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
rss_hf 0x7f83fffc
15/10/2020 15:14:36 dut.10.240.183.254: port config 0 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:14:37 dut.10.240.183.254:
15/10/2020 15:14:37 dut.10.240.183.254: port config 1 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:14:37 dut.10.240.183.254:
15/10/2020 15:14:37 dut.10.240.183.254: show port info all
15/10/2020 15:14:37 dut.10.240.183.254:
********************* Infos for port 0 *********************
MAC address: 68:05:CA:C1:B9:08
Device name: 0000:03:00.0
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 8
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 8
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
********************* Infos for port 1 *********************
MAC address: 68:05:CA:C1:B9:09
Device name: 0000:03:00.1
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 8
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 8
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
15/10/2020 15:14:37 dut.10.240.183.254: start
15/10/2020 15:14:37 dut.10.240.183.254:
rxonly packet forwarding - ports=2 - cores=1 - streams=16 - NUMA support enabled, MP allocation mode: native
Logical Core 2 (socket 0) forwards packets on 16 streams:
RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=1 (socket 0) -> TX P=0/Q=1 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=1 (socket 0) -> TX P=1/Q=1 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=2 (socket 0) -> TX P=0/Q=2 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=2 (socket 0) -> TX P=1/Q=2 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=3 (socket 0) -> TX P=0/Q=3 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=3 (socket 0) -> TX P=1/Q=3 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=4 (socket 0) -> TX P=0/Q=4 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=4 (socket 0) -> TX P=1/Q=4 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=5 (socket 0) -> TX P=0/Q=5 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=5 (socket 0) -> TX P=1/Q=5 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=6 (socket 0) -> TX P=0/Q=6 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=6 (socket 0) -> TX P=1/Q=6 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=7 (socket 0) -> TX P=0/Q=7 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=7 (socket 0) -> TX P=1/Q=7 (socket 0) peer=02:00:00:00:00:01
rxonly packet forwarding packets/burst=32
nb forwarding cores=1 - nb forwarding ports=2
port 0: RX queue number: 8 Tx queue number: 8
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
port 1: RX queue number: 8 Tx queue number: 8
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
15/10/2020 15:14:37 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 proto is 255 / end actions rss queues 0 1 2 3 4 5 6 7 end / end
15/10/2020 15:14:37 dut.10.240.183.254:
Flow rule validated
15/10/2020 15:14:37 dut.10.240.183.254: flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 proto is 255 / end actions rss queues 0 1 2 3 4 5 6 7 end / end
15/10/2020 15:14:37 dut.10.240.183.254:
ice_flow_create(): Succeeded to create (1) flow
Flow rule #0 created
15/10/2020 15:14:39 dut.10.240.183.254: port 0/queue 6: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:55 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0x891a55e6 - RSS queue=0x6 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_NONFRAG - sw ptype: L2_ETHER L3_IPV4 - l2_len=14 - l3_len=20 - Receive queue=0x6
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
port 0/queue 6: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:55 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0x891a55e6 - RSS queue=0x6 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_FRAG - sw ptype: L2_ETHER L3_IPV4 L4_FRAG - l2_len=14 - l3_len=20 - l4_len=0 - Receive queue=0x6
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
15/10/2020 15:14:41 dut.10.240.183.254: port 0/queue 3: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:56 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0x448d2af3 - RSS queue=0x3 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_NONFRAG - sw ptype: L2_ETHER L3_IPV4 - l2_len=14 - l3_len=20 - Receive queue=0x3
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
port 0/queue 5: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:55 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0xcd977f15 - RSS queue=0x5 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_NONFRAG - sw ptype: L2_ETHER L3_IPV4 - l2_len=14 - l3_len=20 - Receive queue=0x5
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
port 0/queue 3: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:55 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0x6f934fb3 - RSS queue=0x3 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_NONFRAG - sw ptype: L2_ETHER L3_IPV4 - l2_len=14 - l3_len=20 - Receive queue=0x3
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
port 0/queue 6: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:55 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0x891a55e6 - RSS queue=0x6 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_ICMP - sw ptype: L2_ETHER L3_IPV4 - l2_len=14 - l3_len=20 - Receive queue=0x6
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
port 0/queue 6: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:55 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0x891a55e6 - RSS queue=0x6 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_NONFRAG - sw ptype: L2_ETHER L3_IPV4 - l2_len=14 - l3_len=20 - Receive queue=0x6
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
port 0/queue 6: received 1 packets
src=52:54:00:40:E5:B6 - dst=00:11:22:33:44:55 - type=0x0800 - length=114 - nb_segs=1 - RSS hash=0x891a55e6 - RSS queue=0x6 - hw ptype: L2_ETHER L3_IPV4_EXT_UNKNOWN L4_NONFRAG - sw ptype: L2_ETHER L3_IPV4 - l2_len=14 - l3_len=20 - Receive queue=0x6
ol_flags: PKT_RX_RSS_HASH PKT_RX_L4_CKSUM_GOOD PKT_RX_IP_CKSUM_GOOD PKT_RX_OUTER_L4_CKSUM_UNKNOWN
15/10/2020 15:14:41 dut.10.240.183.254: kill_all: called by dut and prefix list has value.
15/10/2020 15:14:43 dut.10.240.183.254: Killed
[PEXPECT]#
15/10/2020 15:14:44 dut.10.240.183.254: x86_64-native-linuxapp-gcc/app/dpdk-testpmd -l 1,2,3,4 -n 4 -w 0000:03:00.0 -w 0000:03:00.1 --file-prefix=dpdk_22756_20201015151300 --log-level=ice,7 -- -i --portmask=0x3 --rxq=64 --txq=64 --port-topology=loop
15/10/2020 15:14:45 dut.10.240.183.254: EAL: Detected 72 lcore(s)
EAL: Detected 2 NUMA nodes
EAL: Multi-process socket /var/run/dpdk/dpdk_22756_20201015151300/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: No available hugepages reported in hugepages-1048576kB
EAL: Probing VFIO support...
EAL: VFIO support initialized
EAL: using IOMMU type 1 (Type 1)
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.0 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: Ignore mapping IO port bar(1)
EAL: Ignore mapping IO port bar(4)
EAL: Probe PCI driver: net_ice (8086:1593) device: 0000:03:00.1 (socket 0)
ice_load_pkg_type(): Active package is: 1.3.20.0, ICE COMMS Package
ice_dev_init(): FW 5.2.1656026169 API 1.7
ice_fdir_setup(): FDIR HW Capabilities: fd_fltr_guar = 512, fd_fltr_best_effort = 14336.
__vsi_queues_bind_intr(): queue 0 is binding to vect 65
ice_fdir_setup(): FDIR setup successfully, with programming queue 0.
EAL: No legacy callbacks, legacy socket not created
Interactive-mode selected
testpmd: create a new mbuf pool <mbuf_pool_socket_0>: n=171456, size=2176, socket=0
testpmd: preferred mempool ops selected: ring_mp_mc
Configuring Port 0 (socket 0)
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
Port 0: 68:05:CA:C1:B9:08
Configuring Port 1 (socket 0)
ice_interrupt_handler(): OICR: link state change event
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:14:55 dut.10.240.183.254: port stop all
15/10/2020 15:14:55 dut.10.240.183.254:
Stopping ports...
ice_interrupt_handler(): OICR: link state change event
Port 0: link state change event
Checking link statuses...
ice_interrupt_handler(): OICR: link state change event
Port 1: link state change event
Done
15/10/2020 15:14:55 dut.10.240.183.254: port start all
15/10/2020 15:14:56 dut.10.240.183.254:
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 0: 68:05:CA:C1:B9:08
__vsi_queues_bind_intr(): queue 1 is binding to vect 1
__vsi_queues_bind_intr(): queue 2 is binding to vect 1
__vsi_queues_bind_intr(): queue 3 is binding to vect 1
__vsi_queues_bind_intr(): queue 4 is binding to vect 1
__vsi_queues_bind_intr(): queue 5 is binding to vect 1
__vsi_queues_bind_intr(): queue 6 is binding to vect 1
__vsi_queues_bind_intr(): queue 7 is binding to vect 1
__vsi_queues_bind_intr(): queue 8 is binding to vect 1
__vsi_queues_bind_intr(): queue 9 is binding to vect 1
__vsi_queues_bind_intr(): queue 10 is binding to vect 1
__vsi_queues_bind_intr(): queue 11 is binding to vect 1
__vsi_queues_bind_intr(): queue 12 is binding to vect 1
__vsi_queues_bind_intr(): queue 13 is binding to vect 1
__vsi_queues_bind_intr(): queue 14 is binding to vect 1
__vsi_queues_bind_intr(): queue 15 is binding to vect 1
__vsi_queues_bind_intr(): queue 16 is binding to vect 1
__vsi_queues_bind_intr(): queue 17 is binding to vect 1
__vsi_queues_bind_intr(): queue 18 is binding to vect 1
__vsi_queues_bind_intr(): queue 19 is binding to vect 1
__vsi_queues_bind_intr(): queue 20 is binding to vect 1
__vsi_queues_bind_intr(): queue 21 is binding to vect 1
__vsi_queues_bind_intr(): queue 22 is binding to vect 1
__vsi_queues_bind_intr(): queue 23 is binding to vect 1
__vsi_queues_bind_intr(): queue 24 is binding to vect 1
__vsi_queues_bind_intr(): queue 25 is binding to vect 1
__vsi_queues_bind_intr(): queue 26 is binding to vect 1
__vsi_queues_bind_intr(): queue 27 is binding to vect 1
__vsi_queues_bind_intr(): queue 28 is binding to vect 1
__vsi_queues_bind_intr(): queue 29 is binding to vect 1
__vsi_queues_bind_intr(): queue 30 is binding to vect 1
__vsi_queues_bind_intr(): queue 31 is binding to vect 1
__vsi_queues_bind_intr(): queue 32 is binding to vect 1
__vsi_queues_bind_intr(): queue 33 is binding to vect 1
__vsi_queues_bind_intr(): queue 34 is binding to vect 1
__vsi_queues_bind_intr(): queue 35 is binding to vect 1
__vsi_queues_bind_intr(): queue 36 is binding to vect 1
__vsi_queues_bind_intr(): queue 37 is binding to vect 1
__vsi_queues_bind_intr(): queue 38 is binding to vect 1
__vsi_queues_bind_intr(): queue 39 is binding to vect 1
__vsi_queues_bind_intr(): queue 40 is binding to vect 1
__vsi_queues_bind_intr(): queue 41 is binding to vect 1
__vsi_queues_bind_intr(): queue 42 is binding to vect 1
__vsi_queues_bind_intr(): queue 43 is binding to vect 1
__vsi_queues_bind_intr(): queue 44 is binding to vect 1
__vsi_queues_bind_intr(): queue 45 is binding to vect 1
__vsi_queues_bind_intr(): queue 46 is binding to vect 1
__vsi_queues_bind_intr(): queue 47 is binding to vect 1
__vsi_queues_bind_intr(): queue 48 is binding to vect 1
__vsi_queues_bind_intr(): queue 49 is binding to vect 1
__vsi_queues_bind_intr(): queue 50 is binding to vect 1
__vsi_queues_bind_intr(): queue 51 is binding to vect 1
__vsi_queues_bind_intr(): queue 52 is binding to vect 1
__vsi_queues_bind_intr(): queue 53 is binding to vect 1
__vsi_queues_bind_intr(): queue 54 is binding to vect 1
__vsi_queues_bind_intr(): queue 55 is binding to vect 1
__vsi_queues_bind_intr(): queue 56 is binding to vect 1
__vsi_queues_bind_intr(): queue 57 is binding to vect 1
__vsi_queues_bind_intr(): queue 58 is binding to vect 1
__vsi_queues_bind_intr(): queue 59 is binding to vect 1
__vsi_queues_bind_intr(): queue 60 is binding to vect 1
__vsi_queues_bind_intr(): queue 61 is binding to vect 1
__vsi_queues_bind_intr(): queue 62 is binding to vect 1
__vsi_queues_bind_intr(): queue 63 is binding to vect 1
__vsi_queues_bind_intr(): queue 64 is binding to vect 1
ice_dev_start(): fail to set vsi broadcast
Port 1: 68:05:CA:C1:B9:09
Checking link statuses...
Done
15/10/2020 15:15:01 dut.10.240.183.254: set fwd rxonly
15/10/2020 15:15:01 dut.10.240.183.254:
Set rxonly packet forwarding mode
15/10/2020 15:15:01 dut.10.240.183.254: set verbose 1
15/10/2020 15:15:01 dut.10.240.183.254:
Change verbose level from 0 to 1
15/10/2020 15:15:01 dut.10.240.183.254: port config 0 udp_tunnel_port add vxlan 4789
15/10/2020 15:15:01 dut.10.240.183.254:
15/10/2020 15:15:01 dut.10.240.183.254: port config 1 udp_tunnel_port add vxlan 4789
15/10/2020 15:15:01 dut.10.240.183.254:
15/10/2020 15:15:01 dut.10.240.183.254: port config all rss all
15/10/2020 15:15:01 dut.10.240.183.254:
Port 0 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
Port 1 modified RSS hash function based on hardware support,requested:0x7f83fffc configured:0x7ffc
rss_hf 0x7f83fffc
15/10/2020 15:15:01 dut.10.240.183.254: port config 0 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:15:01 dut.10.240.183.254:
15/10/2020 15:15:01 dut.10.240.183.254: port config 1 rss-hash-key ipv4 1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd1234abcd
15/10/2020 15:15:01 dut.10.240.183.254:
15/10/2020 15:15:01 dut.10.240.183.254: show port info all
15/10/2020 15:15:01 dut.10.240.183.254:
********************* Infos for port 0 *********************
MAC address: 68:05:CA:C1:B9:08
Device name: 0000:03:00.0
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 64
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 64
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
********************* Infos for port 1 *********************
MAC address: 68:05:CA:C1:B9:09
Device name: 0000:03:00.1
Driver name: net_ice
Firmware-version: 2.20 0x800047c3 1.2832.0
Devargs:
Connect to socket: 0
memory allocation on the socket: 0
Link status: up
Link speed: 25 Gbps
Link duplex: full-duplex
MTU: 1500
Promiscuous mode: enabled
Allmulticast mode: disabled
Maximum number of MAC addresses: 64
Maximum number of MAC addresses of hash filtering: 0
VLAN offload:
strip off, filter off, extend off, qinq strip off
Hash key size in bytes: 52
Redirection table size: 512
Supported RSS offload flow types:
ipv4
ipv4-frag
ipv4-tcp
ipv4-udp
ipv4-sctp
ipv4-other
ipv6
ipv6-frag
ipv6-tcp
ipv6-udp
ipv6-sctp
ipv6-other
l2_payload
Minimum size of RX buffer: 1024
Maximum configurable length of RX packet: 9728
Maximum configurable size of LRO aggregated packet: 0
Current number of RX queues: 64
Max possible RX queues: 64
Max possible number of RXDs per queue: 4096
Min possible number of RXDs per queue: 64
RXDs number alignment: 32
Current number of TX queues: 64
Max possible TX queues: 64
Max possible number of TXDs per queue: 4096
Min possible number of TXDs per queue: 64
TXDs number alignment: 32
Max segment number per packet: 0
Max segment number per MTU/TSO: 0
15/10/2020 15:15:01 TestCVLFdir: Test Case test_invalid_parameters_of_rss_queues Result PASSED:
15/10/2020 15:15:01 dut.10.240.183.254: flow flush 0
15/10/2020 15:15:02 dut.10.240.183.254:
testpmd>
15/10/2020 15:15:02 dut.10.240.183.254: flow flush 1
15/10/2020 15:15:04 dut.10.240.183.254:
testpmd>
15/10/2020 15:15:04 dut.10.240.183.254: clear port stats all
15/10/2020 15:15:05 dut.10.240.183.254:
NIC statistics for port 0 cleared
NIC statistics for port 1 cleared
testpmd>
15/10/2020 15:15:05 dut.10.240.183.254: stop
15/10/2020 15:15:05 dut.10.240.183.254:
Packet forwarding not started
15/10/2020 15:15:05 TestCVLFdir: Test Case test_negative_validation Begin
15/10/2020 15:15:05 dut.10.240.183.254:
15/10/2020 15:15:05 tester:
15/10/2020 15:15:05 dut.10.240.183.254: start
15/10/2020 15:15:05 dut.10.240.183.254:
rxonly packet forwarding - ports=2 - cores=1 - streams=128 - NUMA support enabled, MP allocation mode: native
Logical Core 2 (socket 0) forwards packets on 128 streams:
RX P=0/Q=0 (socket 0) -> TX P=0/Q=0 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=0 (socket 0) -> TX P=1/Q=0 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=1 (socket 0) -> TX P=0/Q=1 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=1 (socket 0) -> TX P=1/Q=1 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=2 (socket 0) -> TX P=0/Q=2 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=2 (socket 0) -> TX P=1/Q=2 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=3 (socket 0) -> TX P=0/Q=3 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=3 (socket 0) -> TX P=1/Q=3 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=4 (socket 0) -> TX P=0/Q=4 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=4 (socket 0) -> TX P=1/Q=4 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=5 (socket 0) -> TX P=0/Q=5 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=5 (socket 0) -> TX P=1/Q=5 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=6 (socket 0) -> TX P=0/Q=6 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=6 (socket 0) -> TX P=1/Q=6 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=7 (socket 0) -> TX P=0/Q=7 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=7 (socket 0) -> TX P=1/Q=7 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=8 (socket 0) -> TX P=0/Q=8 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=8 (socket 0) -> TX P=1/Q=8 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=9 (socket 0) -> TX P=0/Q=9 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=9 (socket 0) -> TX P=1/Q=9 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=10 (socket 0) -> TX P=0/Q=10 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=10 (socket 0) -> TX P=1/Q=10 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=11 (socket 0) -> TX P=0/Q=11 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=11 (socket 0) -> TX P=1/Q=11 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=12 (socket 0) -> TX P=0/Q=12 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=12 (socket 0) -> TX P=1/Q=12 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=13 (socket 0) -> TX P=0/Q=13 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=13 (socket 0) -> TX P=1/Q=13 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=14 (socket 0) -> TX P=0/Q=14 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=14 (socket 0) -> TX P=1/Q=14 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=15 (socket 0) -> TX P=0/Q=15 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=15 (socket 0) -> TX P=1/Q=15 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=16 (socket 0) -> TX P=0/Q=16 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=16 (socket 0) -> TX P=1/Q=16 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=17 (socket 0) -> TX P=0/Q=17 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=17 (socket 0) -> TX P=1/Q=17 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=18 (socket 0) -> TX P=0/Q=18 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=18 (socket 0) -> TX P=1/Q=18 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=19 (socket 0) -> TX P=0/Q=19 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=19 (socket 0) -> TX P=1/Q=19 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=20 (socket 0) -> TX P=0/Q=20 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=20 (socket 0) -> TX P=1/Q=20 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=21 (socket 0) -> TX P=0/Q=21 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=21 (socket 0) -> TX P=1/Q=21 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=22 (socket 0) -> TX P=0/Q=22 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=22 (socket 0) -> TX P=1/Q=22 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=23 (socket 0) -> TX P=0/Q=23 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=23 (socket 0) -> TX P=1/Q=23 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=24 (socket 0) -> TX P=0/Q=24 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=24 (socket 0) -> TX P=1/Q=24 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=25 (socket 0) -> TX P=0/Q=25 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=25 (socket 0) -> TX P=1/Q=25 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=26 (socket 0) -> TX P=0/Q=26 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=26 (socket 0) -> TX P=1/Q=26 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=27 (socket 0) -> TX P=0/Q=27 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=27 (socket 0) -> TX P=1/Q=27 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=28 (socket 0) -> TX P=0/Q=28 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=28 (socket 0) -> TX P=1/Q=28 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=29 (socket 0) -> TX P=0/Q=29 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=29 (socket 0) -> TX P=1/Q=29 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=30 (socket 0) -> TX P=0/Q=30 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=30 (socket 0) -> TX P=1/Q=30 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=31 (socket 0) -> TX P=0/Q=31 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=31 (socket 0) -> TX P=1/Q=31 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=32 (socket 0) -> TX P=0/Q=32 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=32 (socket 0) -> TX P=1/Q=32 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=33 (socket 0) -> TX P=0/Q=33 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=33 (socket 0) -> TX P=1/Q=33 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=34 (socket 0) -> TX P=0/Q=34 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=34 (socket 0) -> TX P=1/Q=34 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=35 (socket 0) -> TX P=0/Q=35 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=35 (socket 0) -> TX P=1/Q=35 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=36 (socket 0) -> TX P=0/Q=36 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=36 (socket 0) -> TX P=1/Q=36 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=37 (socket 0) -> TX P=0/Q=37 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=37 (socket 0) -> TX P=1/Q=37 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=38 (socket 0) -> TX P=0/Q=38 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=38 (socket 0) -> TX P=1/Q=38 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=39 (socket 0) -> TX P=0/Q=39 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=39 (socket 0) -> TX P=1/Q=39 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=40 (socket 0) -> TX P=0/Q=40 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=40 (socket 0) -> TX P=1/Q=40 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=41 (socket 0) -> TX P=0/Q=41 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=41 (socket 0) -> TX P=1/Q=41 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=42 (socket 0) -> TX P=0/Q=42 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=42 (socket 0) -> TX P=1/Q=42 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=43 (socket 0) -> TX P=0/Q=43 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=43 (socket 0) -> TX P=1/Q=43 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=44 (socket 0) -> TX P=0/Q=44 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=44 (socket 0) -> TX P=1/Q=44 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=45 (socket 0) -> TX P=0/Q=45 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=45 (socket 0) -> TX P=1/Q=45 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=46 (socket 0) -> TX P=0/Q=46 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=46 (socket 0) -> TX P=1/Q=46 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=47 (socket 0) -> TX P=0/Q=47 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=47 (socket 0) -> TX P=1/Q=47 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=48 (socket 0) -> TX P=0/Q=48 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=48 (socket 0) -> TX P=1/Q=48 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=49 (socket 0) -> TX P=0/Q=49 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=49 (socket 0) -> TX P=1/Q=49 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=50 (socket 0) -> TX P=0/Q=50 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=50 (socket 0) -> TX P=1/Q=50 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=51 (socket 0) -> TX P=0/Q=51 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=51 (socket 0) -> TX P=1/Q=51 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=52 (socket 0) -> TX P=0/Q=52 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=52 (socket 0) -> TX P=1/Q=52 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=53 (socket 0) -> TX P=0/Q=53 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=53 (socket 0) -> TX P=1/Q=53 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=54 (socket 0) -> TX P=0/Q=54 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=54 (socket 0) -> TX P=1/Q=54 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=55 (socket 0) -> TX P=0/Q=55 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=55 (socket 0) -> TX P=1/Q=55 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=56 (socket 0) -> TX P=0/Q=56 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=56 (socket 0) -> TX P=1/Q=56 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=57 (socket 0) -> TX P=0/Q=57 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=57 (socket 0) -> TX P=1/Q=57 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=58 (socket 0) -> TX P=0/Q=58 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=58 (socket 0) -> TX P=1/Q=58 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=59 (socket 0) -> TX P=0/Q=59 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=59 (socket 0) -> TX P=1/Q=59 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=60 (socket 0) -> TX P=0/Q=60 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=60 (socket 0) -> TX P=1/Q=60 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=61 (socket 0) -> TX P=0/Q=61 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=61 (socket 0) -> TX P=1/Q=61 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=62 (socket 0) -> TX P=0/Q=62 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=62 (socket 0) -> TX P=1/Q=62 (socket 0) peer=02:00:00:00:00:01
RX P=0/Q=63 (socket 0) -> TX P=0/Q=63 (socket 0) peer=02:00:00:00:00:00
RX P=1/Q=63 (socket 0) -> TX P=1/Q=63 (socket 0) peer=02:00:00:00:00:01
rxonly packet forwarding packets/burst=32
nb forwarding cores=1 - nb forwarding ports=2
port 0: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
port 1: RX queue number: 64 Tx queue number: 64
Rx offloads=0x0 Tx offloads=0x10000
RX queue: 0
RX desc=1024 - RX free threshold=32
RX threshold registers: pthresh=0 hthresh=0 wthresh=0
RX Offloads=0x0
TX queue: 0
TX desc=1024 - TX free threshold=32
TX threshold registers: pthresh=32 hthresh=0 wthresh=0
TX offloads=0x10000 - TX RS bit threshold=32
15/10/2020 15:15:05 dut.10.240.183.254: flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / and actions end
15/10/2020 15:15:05 dut.10.240.183.254:
Bad arguments
15/10/2020 15:15:05 dut.10.240.183.254: flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 2 3 end / rss / end
15/10/2020 15:15:05 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffc3cb26e68, Invalid action number: Invalid argument
15/10/2020 15:15:05 dut.10.240.183.254: flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions passthru / mark id 4294967296 / end
15/10/2020 15:15:05 dut.10.240.183.254:
Bad arguments
15/10/2020 15:15:05 dut.10.240.183.254: flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tc is 4 / end actions queue index 1 / end
15/10/2020 15:15:05 dut.10.240.183.254:
Bad arguments
15/10/2020 15:15:05 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions queue index 64 / end
15/10/2020 15:15:05 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffc3cb26e68, Invalid action type or queue number: Invalid argument
15/10/2020 15:15:05 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 end / end
15/10/2020 15:15:05 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffc3cb26e68, Invalid action type or queue number: Invalid argument
15/10/2020 15:15:05 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 0 end / end
15/10/2020 15:15:06 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffc3cb26e68, Invalid action type or queue number: Invalid argument
15/10/2020 15:15:06 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues end / end
15/10/2020 15:15:06 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffc3cb26e68, Invalid action type or queue number: Invalid argument
15/10/2020 15:15:06 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 5 end / end
15/10/2020 15:15:06 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffc3cb26e68, Discontinuous queue region: Invalid argument
15/10/2020 15:15:06 dut.10.240.183.254: flow validate 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 63 64 end / end
15/10/2020 15:15:06 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 16 (specific action): cause: 0x7ffc3cb26e68, Invalid queue region indexes: Invalid argument
15/10/2020 15:15:06 dut.10.240.183.254: flow validate 0 ingress pattern eth / ipv4 / udp / gtpu teid is 0x12345678 / gtp_psc qfi is 0x100 / end actions queue index 1 / end
15/10/2020 15:15:06 dut.10.240.183.254:
Bad arguments
15/10/2020 15:15:06 dut.10.240.183.254: flow validate 0 ingress pattern eth / ipv4 / udp / gtpu teid is 0x100000000 / gtp_psc qfi is 0x5 / end actions queue index 2 / end
15/10/2020 15:15:06 dut.10.240.183.254:
Bad arguments
15/10/2020 15:15:06 dut.10.240.183.254: flow validate 0 ingress pattern eth / ipv4 / udp / gtpu teid is 0x100000000 / end actions queue index 1 / end
15/10/2020 15:15:06 dut.10.240.183.254:
Bad arguments
15/10/2020 15:15:06 dut.10.240.183.254: flow validate 2 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions queue index 1 / end
15/10/2020 15:15:06 dut.10.240.183.254:
port_flow_complain(): Caught PMD error type 1 (cause unspecified): No such device: No such device
15/10/2020 15:15:06 dut.10.240.183.254: flow list 0
15/10/2020 15:15:06 dut.10.240.183.254:
15/10/2020 15:15:06 TestCVLFdir: Test Case test_negative_validation Result PASSED:
15/10/2020 15:15:06 dut.10.240.183.254: flow flush 0
15/10/2020 15:15:07 dut.10.240.183.254:
testpmd>
15/10/2020 15:15:07 dut.10.240.183.254: flow flush 1
15/10/2020 15:15:08 dut.10.240.183.254:
testpmd>
15/10/2020 15:15:08 dut.10.240.183.254: clear port stats all
15/10/2020 15:15:10 dut.10.240.183.254:
NIC statistics for port 0 cleared
NIC statistics for port 1 cleared
testpmd>
15/10/2020 15:15:10 dut.10.240.183.254: stop
15/10/2020 15:15:10 dut.10.240.183.254:
Telling cores to ...
Waiting for lcores to finish...
---------------------- Forward statistics for port 0 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
---------------------- Forward statistics for port 1 ----------------------
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
----------------------------------------------------------------------------
+++++++++++++++ Accumulated forward statistics for all ports+++++++++++++++
RX-packets: 0 RX-dropped: 0 RX-total: 0
TX-packets: 0 TX-dropped: 0 TX-total: 0
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Done.
15/10/2020 15:15:10 dts:
TEST SUITE ENDED: TestCVLFdir
^ permalink raw reply [flat|nested] 4+ messages in thread
* [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551
@ 2020-10-15 9:48 sunqin
2020-10-15 5:14 ` Peng, Yuan
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: sunqin @ 2020-10-15 9:48 UTC (permalink / raw)
To: dts; +Cc: sunqin
According to dpdk commit cb97e595d9d3b316690c8d5ac688240d2ba1e551 to
modify log validation for wrong action
Signed-off-by: sunqin <qinx.sun@intel.com>
---
test_plans/cvl_fdir_test_plan.rst | 8 ++++----
tests/TestSuite_cvl_fdir.py | 14 +++++++-------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/test_plans/cvl_fdir_test_plan.rst b/test_plans/cvl_fdir_test_plan.rst
index 0e1521f..740cb37 100644
--- a/test_plans/cvl_fdir_test_plan.rst
+++ b/test_plans/cvl_fdir_test_plan.rst
@@ -610,7 +610,7 @@ Note: there may be error message change.
get the message::
- Invalid input action: Invalid argument
+ 'error' in message
Discontinuous queues::
@@ -2939,7 +2939,7 @@ Subcase 1: invalid parameters of queue index
Failed to create flow, report message::
- Invalid queue for FDIR.: Invalid argument
+ 'error' in message
2. check there is no rule listed.
@@ -3053,7 +3053,7 @@ Subcase 6: conflicted rules
or::
- Invalid input action number: Invalid argument
+ 'error' in message
3. check there is only one rule listed.
@@ -3066,7 +3066,7 @@ Subcase 7: conflicted actions
Failed to create flow, report message::
- Invalid input action: Invalid argument
+ 'error' in message
2. check there is no rule listed.
diff --git a/tests/TestSuite_cvl_fdir.py b/tests/TestSuite_cvl_fdir.py
index e5a9c71..fd005b3 100644
--- a/tests/TestSuite_cvl_fdir.py
+++ b/tests/TestSuite_cvl_fdir.py
@@ -2428,7 +2428,7 @@ class TestCVLFdir(TestCase):
check_stats=False, check_msg='Bad arguments')
self.validate_fdir_rule(
'flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 2 3 end / rss / end',
- check_stats=False, check_msg='Invalid input action number: Invalid argument')
+ check_stats=False, check_msg='error')
self.validate_fdir_rule(
'flow validate 0 ingress pattern eth / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions passthru / mark id 4294967296 / end',
check_stats=False, check_msg='Bad arguments')
@@ -2580,7 +2580,7 @@ class TestCVLFdir(TestCase):
def test_invalid_parameters_of_queue_index(self):
rule = "flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions queue index 64 / end"
out = self.dut.send_command(rule, timeout=1)
- self.verify("Invalid input action: Invalid argument" in out, "failed with output: %s" % out)
+ self.verify("error" in out, "failed with output: %s" % out)
self.check_fdir_rule(port_id=0, stats=False)
def test_invalid_parameters_of_rss_queues(self):
@@ -2588,11 +2588,11 @@ class TestCVLFdir(TestCase):
"flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 end / end",
"flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 0 end / end",
"flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues end / end"]
- self.create_fdir_rule(rule=rule1, check_stats=False, msg='Invalid input action: Invalid argument')
+ self.create_fdir_rule(rule=rule1, check_stats=False, msg='error')
rule2 = 'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 1 2 3 5 end / end'
- self.create_fdir_rule(rule2, check_stats=False, msg='Invalid input action: Invalid argument')
+ self.create_fdir_rule(rule2, check_stats=False, msg='error')
rule3 = 'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 proto is 255 ttl is 2 tos is 4 / end actions rss queues 63 64 end / end'
- self.create_fdir_rule(rule3, check_stats=False, msg='Invalid input action: Invalid argument')
+ self.create_fdir_rule(rule3, check_stats=False, msg='error')
try:
# restart testpmd
self.dut.send_expect("quit", "# ")
@@ -2655,13 +2655,13 @@ class TestCVLFdir(TestCase):
'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2021 / end actions mark / end',
'flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv6 dst is CDCD:910A:2222:5498:8475:1111:3900:2020 src is 2001::2 / udp src is 22 dst is 23 / end actions queue index 1 / mark / end']
self.create_fdir_rule(rule2[0:4], check_stats=False, msg="Rule already exists!: File exists", validate=False)
- self.create_fdir_rule(rule2[4:7], check_stats=False, msg="Invalid input action number: Invalid argument", validate=False)
+ self.create_fdir_rule(rule2[4:7], check_stats=False, msg="error", validate=False)
self.create_fdir_rule(rule2[7:], check_stats=False, msg="Invalid input set: Invalid argument", validate=False)
self.check_fdir_rule(stats=True, rule_list=rule_li)
def test_conflicted_actions(self):
rule1 = "flow create 0 ingress pattern eth dst is 00:11:22:33:44:55 / ipv4 src is 192.168.0.20 dst is 192.168.0.21 ttl is 2 tos is 4 / end actions queue index 1 / rss queues 2 3 end / end"
- self.create_fdir_rule(rule1, check_stats=False, msg="Invalid input action number: Invalid argument")
+ self.create_fdir_rule(rule1, check_stats=False, msg="error")
self.check_fdir_rule(stats=False)
def test_void_action(self):
--
2.17.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551
2020-10-15 9:48 [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551 sunqin
2020-10-15 5:14 ` Peng, Yuan
2020-10-15 7:04 ` Sun, QinX
@ 2020-10-16 6:56 ` Ma, LihongX
2 siblings, 0 replies; 4+ messages in thread
From: Ma, LihongX @ 2020-10-16 6:56 UTC (permalink / raw)
To: Sun, QinX, dts; +Cc: Sun, QinX
> -----Original Message-----
> From: dts <dts-bounces@dpdk.org> On Behalf Of sunqin
> Sent: Thursday, October 15, 2020 5:49 PM
> To: dts@dpdk.org
> Cc: Sun, QinX <qinx.sun@intel.com>
> Subject: [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log
> validation for wrong action according to the change of dpdk, dpdk commit
> id:cb97e595d9d3b316690c8d5ac688240d2ba1e551
>
> According to dpdk commit cb97e595d9d3b316690c8d5ac688240d2ba1e551 to modify
> log validation for wrong action
>
> Signed-off-by: sunqin <qinx.sun@intel.com>
> ---
The subject is the summarize of your patch, now the title is too long.
The commit id information put in comments is enough.
BTW: the format of the subject is like : [dts] [PATCH V1] tests/cvl_fdir: modify the log validation for wrong action according to the change of dpdk
Regards,
Ma,lihong
^ permalink raw reply [flat|nested] 4+ messages in thread
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2020-10-15 9:48 [dts] [PATCH V1] tests/TestSuite_cvl_fdir.py modify the log validation for wrong action according to the change of dpdk, dpdk commit id:cb97e595d9d3b316690c8d5ac688240d2ba1e551 sunqin
2020-10-15 5:14 ` Peng, Yuan
2020-10-15 7:04 ` Sun, QinX
2020-10-16 6:56 ` Ma, LihongX
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