From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 96F97AD9C for ; Wed, 4 Feb 2015 07:47:39 +0100 (CET) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP; 03 Feb 2015 22:47:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,517,1418112000"; d="scan'208";a="680601632" Received: from kmsmsx152.gar.corp.intel.com ([172.21.73.87]) by orsmga002.jf.intel.com with ESMTP; 03 Feb 2015 22:47:37 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by KMSMSX152.gar.corp.intel.com (172.21.73.87) with Microsoft SMTP Server (TLS) id 14.3.195.1; Wed, 4 Feb 2015 14:47:34 +0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.253]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.129]) with mapi id 14.03.0195.001; Wed, 4 Feb 2015 14:47:34 +0800 From: "Qiu, Michael" To: "Liu, Yong" , "dts@dpdk.org" Thread-Topic: [dts] [PATCH v2 1/4] framework: add new module for load port configuration file Thread-Index: AQHQQEYHTIqdk3hpP0KKpUay+mdenw== Date: Wed, 4 Feb 2015 06:47:33 +0000 Message-ID: <533710CFB86FA344BFBF2D6802E60286CD4616@SHSMSX101.ccr.corp.intel.com> References: <1423032214-19856-1-git-send-email-yong.liu@intel.com> <1423032214-19856-2-git-send-email-yong.liu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dts] [PATCH v2 1/4] framework: add new module for load port configuration file X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Feb 2015 06:47:40 -0000 On 2/4/2015 2:44 PM, Yong Liu wrote:=0A= > Config module will load port configuration and parse port parameter.=0A= > Port configuration will be used in the process of setting up DUT.=0A= > User can assign port mac, numa or tester peer pci address of DUT port.=0A= >=0A= > Signed-off-by: Marvinliu =0A= > ---=0A= > conf/ports.cfg | 9 +++++=0A= > framework/config.py | 96 +++++++++++++++++++++++++++++++++++++++++++++++= ++++++=0A= > 2 files changed, 105 insertions(+)=0A= > create mode 100644 conf/ports.cfg=0A= > create mode 100755 framework/config.py=0A= >=0A= > diff --git a/conf/ports.cfg b/conf/ports.cfg=0A= > new file mode 100644=0A= > index 0000000..55e26d8=0A= > --- /dev/null=0A= > +++ b/conf/ports.cfg=0A= > @@ -0,0 +1,9 @@=0A= > +# DUT Port Configuration=0A= > +# [DUT IP]=0A= > +# ports=3D=0A= > +# pci=3DPci BDF,intf=3DKernel interface;=0A= > +# pci=3DPci BDF,mac=3DMac address,peer=3DTester Pci BDF,numa=3DPort = Numa =0A= > +[DUT IP]=0A= > +ports =3D =0A= > + pci=3DXX:XX.X,intf=3Deth0=0A= > + pci=3DYY:YY.Y,mac=3DXX:XX:XX:XX:XX:XX,peer=3DZZ:ZZ.Z,numa=3D0=0A= > diff --git a/framework/config.py b/framework/config.py=0A= > new file mode 100755=0A= > index 0000000..dc4f944=0A= > --- /dev/null=0A= > +++ b/framework/config.py=0A= > @@ -0,0 +1,96 @@=0A= > +# BSD LICENSE=0A= > +#=0A= > +# Copyright(c) 2010-2014 Intel Corporation. All rights reserved.=0A= > +# All rights reserved.=0A= > +#=0A= > +# Redistribution and use in source and binary forms, with or without=0A= > +# modification, are permitted provided that the following conditions=0A= > +# are met:=0A= > +#=0A= > +# * Redistributions of source code must retain the above copyright=0A= > +# notice, this list of conditions and the following disclaimer.=0A= > +# * Redistributions in binary form must reproduce the above copyright= =0A= > +# notice, this list of conditions and the following disclaimer in=0A= > +# the documentation and/or other materials provided with the=0A= > +# distribution.=0A= > +# * Neither the name of Intel Corporation nor the names of its=0A= > +# contributors may be used to endorse or promote products derived=0A= > +# from this software without specific prior written permission.=0A= > +#=0A= > +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS=0A= > +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT=0A= > +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR= =0A= > +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT= =0A= > +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,= =0A= > +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT=0A= > +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,= =0A= > +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY= =0A= > +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT=0A= > +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE= =0A= > +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.= =0A= > +=0A= > +"""=0A= > +Generic port and crbs configuration file load function=0A= > +"""=0A= > +=0A= > +import ConfigParser # config parse module=0A= > +import argparse # prase arguments module=0A= > +=0A= > +portconf =3D "../conf/ports.cfg"=0A= > +crbconf =3D "../conf/crbs.cfg"=0A= > +=0A= > +=0A= > +class UserConf():=0A= > +=0A= > + def __init__(self, port_conf=3Dportconf, crb_conf=3Dcrbconf):=0A= > + self.port_config =3D port_conf=0A= > + self.crb_config =3D crb_conf=0A= > + self.ports_cfg =3D {}=0A= > + try:=0A= > + self.port_conf =3D ConfigParser.SafeConfigParser()=0A= > + self.port_conf.read(self.port_config)=0A= > + except Exception as e:=0A= > + print "FAILED LOADING PORT CONFIG!!!"=0A= > +=0A= > + def load_ports_config(self, crbIP):=0A= > + ports =3D []=0A= > + for crb in self.port_conf.sections():=0A= > + if crb !=3D crbIP:=0A= > + continue=0A= > + ports =3D [port.strip()=0A= > + for port in self.port_conf.get(crb, 'ports').split(= ';')]=0A= > +=0A= > + for port in ports:=0A= > + port_cfg =3D self.parse_port_param(port)=0A= > + if 'pci' not in port_cfg:=0A= > + print "INVALID CONFIG FOR NO PCI ADDRESS!!!"=0A= > + keys =3D port_cfg.keys()=0A= > + keys.remove('pci')=0A= > + self.ports_cfg[port_cfg['pci']] =3D {key: port_cfg[key] for = key in keys}=0A= > +=0A= > + def check_port_available(self, pci_addr):=0A= > + if pci_addr in self.ports_cfg.keys():=0A= > + return True=0A= > + else:=0A= > + return False=0A= > +=0A= > + def parse_port_param(self, port):=0A= > + portDict =3D dict()=0A= > +=0A= > + for param in port.split(','):=0A= > + (key, _, value) =3D param.partition('=3D')=0A= > + if key =3D=3D 'numa':=0A= > + portDict[key] =3D int(value)=0A= > + else:=0A= > + portDict[key] =3D value=0A= > + return portDict=0A= > +=0A= > +=0A= > +if __name__ =3D=3D '__main__':=0A= > + parser =3D argparse.ArgumentParser(description=3D"Load DTS configura= tion files")=0A= > + parser.add_argument("-p", "--portconf", default=3Dportconf)=0A= > + parser.add_argument("-c", "--crbconf", default=3Dcrbconf)=0A= > + args =3D parser.parse_args()=0A= > + conf =3D UserConf()=0A= > + conf.load_ports_config('192.168.1.1')=0A= > + conf.check_port_available('0000:86:00.0')=0A= Acked-by: Michael Qiu =0A=