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From: "Liu, Yong" <yong.liu@intel.com>
To: xueqin.lin <xlin15@ecsmtp.sh.intel.com>, "dts@dpdk.org" <dts@dpdk.org>
CC: "Lin, Xueqin" <xueqin.lin@intel.com>
Thread-Topic: [dts][PATCH] tests_ftag: fix expected output time when
 striping port glort ID
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Date: Thu, 18 Aug 2016 07:42:55 +0000
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Subject: Re: [dts] [PATCH] tests_ftag: fix expected output time when
 striping port glort ID
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Thanks, applied.

> -----Original Message-----
> From: xueqin.lin [mailto:xlin15@ecsmtp.sh.intel.com]
> Sent: Thursday, August 18, 2016 2:16 PM
> To: Liu, Yong; dts@dpdk.org
> Cc: Lin, Xueqin
> Subject: [dts][PATCH] tests_ftag: fix expected output time when striping
> port glort ID
>=20
> From: Xueqin Lin <xueqin.lin@intel.com>
>=20
> It is impossible to wait some long time for expected output, just fix as
> default value.
>=20
>=20
> diff --git a/nics/rrc.py b/nics/rrc.py
> index 62dc8d2..a6ac175 100644
> --- a/nics/rrc.py
> +++ b/nics/rrc.py
> @@ -259,7 +259,7 @@ class RedRockCanyou(NetDevice):
>              return None
>          else:
>              port_value =3D res.group(2)
> -        out =3D self.ctrl_crb.send_expect("show stacking logical-port al=
l",
> "<0>%",10000)
> +        out =3D self.ctrl_crb.send_expect("show stacking logical-port al=
l",
> "<0>%")
>          pattern =3D r"([0-9a-z]{6})+(\s)+(%s)+" %port_value
>          s =3D re.compile(pattern)
>          res =3D s.search(out)
> --
> 2.5.5