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Mon, 20 Nov 2017 11:09:51 +0800 From: "Liu, Yong" To: "Zhang, Yuwei1" , "dts@dpdk.org" CC: "Zhang, Yuwei1" Thread-Topic: [dts] [PATCH V2] Add a function used to verify keep packets' order feature Thread-Index: AQHTXJFT9HQlxNxFgUu5R95HyrUWvKMcoCuA Date: Mon, 20 Nov 2017 03:09:50 +0000 Message-ID: <86228AFD5BCD8E4EBFD2B90117B5E81E62F1A94A@SHSMSX103.ccr.corp.intel.com> References: <20171113150818.7960-1-yuwei1.zhang@intel.com> In-Reply-To: <20171113150818.7960-1-yuwei1.zhang@intel.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMDcxYzFmMjktNTQ2Zi00NDY3LWJjNDktNzRiNTU2MjVkYjNhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJjbktvbEIrS0RhS0JtNG5WODZSS2R2c0RCdDRvUHQ3TUFaczgybVVIR1hhdThKbzY4SFdSa2gwOUhpTEV1OUxyIn0= x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dts] [PATCH V2] Add a function used to verify keep packets' order feature X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Nov 2017 03:09:55 -0000 Thanks Yuwei, some comments are inline. > -----Original Message----- > From: dts [mailto:dts-bounces@dpdk.org] On Behalf Of Yuwei Zhang > Sent: Monday, November 13, 2017 11:08 PM > To: dts@dpdk.org > Cc: Zhang, Yuwei1 > Subject: [dts] [PATCH V2] Add a function used to verify keep packets' > order feature >=20 > Signed-off-by: Yuwei Zhang > --- > framework/etgen.py | 74 +++++++++++++++++++++++------------------------= - > ----- > framework/tester.py | 7 +++++ > 2 files changed, 39 insertions(+), 42 deletions(-) >=20 > diff --git a/framework/etgen.py b/framework/etgen.py > index b19ae84..373e420 100644 > --- a/framework/etgen.py > +++ b/framework/etgen.py > @@ -558,6 +558,38 @@ class IxiaPacketGenerator(SSHConnection): > rxPortlist, txPortlist =3D self._configure_everything(port_list, > rate_percent) > return self.get_transmission_results(rxPortlist, txPortlist, > delay) >=20 > + def is_packet_ordered(self, port_list, delay): Please add some descriptions for this function, not everyone familiar with = the concept.=20 Please also add the limitation description here like only one stream is sup= ported.=20 > + rxPortlist, txPortlist =3D self.prepare_port_list(port_list) > + self.prepare_ixia_for_transmission(txPortlist, rxPortlist) > + self.send_expect('port config -receiveMode [expr > $::portCapture|$::portRxFirstTimeStamp|$::portRxSequenceChecking|$::portR= x > ModeWidePacketGroup]', '%') Please check whether portCapture and portRxFirstTimeStamp is needed in sequ= ence check function. > + self.send_expect('port config -autonegotiate true', '%') > + self.send_expect('ixWritePortsToHardware portList', '%') > + self.send_expect('set streamId 1', '%') > + self.send_expect('stream setDefault', '%') > + self.send_expect('ixStartPortPacketGroups %d %d %d' % > (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%') > + self.send_expect('ixStartTransmit portList', '%') > + self.send_expect('after 1000 * %d' % delay, '%') > + self.send_expect('ixStopTransmit portList', '%') > + self.send_expect('ixStopPortPacketGroups %d %d %d' % (self.chasI= d, > self.ports[0]['card'], self.ports[0]['port']), '%') > + self.send_expect('after 1000 * %d' % delay, '%') Look like add delay here is useless. > + self.send_expect('packetGroupStats get %d %d %d 1 1' % > (self.chasId, self.ports[0]['card'], self.ports[0]['port']), '%') > + self.send_expect('packetroupStats getGroup 1', '%') > + self.send_expect('set reverseSequenceError [packetGroupStats cge= t > -reverseSequenceError]]', '%') > + output =3D self.send_expect('puts $reverseSequenceError', '%') > + return int(output[:-2]) > + > def _configure_everything(self, port_list, rate_percent, > latency=3DFalse): > """ > Prepare and configure IXIA ports for performance test. >=20 > diff --git a/framework/tester.py b/framework/tester.py > index 9208b0e..1c854d7 100644 > --- a/framework/tester.py > +++ b/framework/tester.py > @@ -502,6 +502,13 @@ class Tester(Crb): > return None > return self.packet_gen.throughput(portList, rate_percent) >=20 > + def verify_packet_order(self, portList, delay): > + if self.check_port_list(portList, 'ixia'): > + return self.ixia_packet_gen.is_packet_ordered(portList, dela= y) > + else: > + self.logger.warning("Only ixia port support check verify > packet order function") > + return False > + > def run_rfc2544(self, portlist, delay=3D120, permit_loss_rate=3D0): > """ > test_rate: the line rate we are going to test. > -- > 2.14.1.windows.1