From: "Tu, Lijuan" <lijuan.tu@intel.com>
To: David Wilder <dwilder@us.ibm.com>, "dts@dpdk.org" <dts@dpdk.org>
Cc: "pradeep@us.ibm.com" <pradeep@us.ibm.com>,
"wilder@us.ibm.com" <wilder@us.ibm.com>
Subject: Re: [dts] [PATCH V1] tests/coremask: correct Master lcore
Date: Mon, 15 Apr 2019 22:35:42 +0000 [thread overview]
Message-ID: <8CE3E05A3F976642AAB0F4675D0AD20E0BA626F1@SHSMSX101.ccr.corp.intel.com> (raw)
In-Reply-To: <20190327212145.1978-1-dwilder@us.ibm.com>
Applied, thanks
> -----Original Message-----
> From: dts [mailto:dts-bounces@dpdk.org] On Behalf Of David Wilder
> Sent: Wednesday, March 27, 2019 2:22 PM
> To: dts@dpdk.org
> Cc: pradeep@us.ibm.com; wilder@us.ibm.com
> Subject: [dts] [PATCH V1] tests/coremask: correct Master lcore
>
> The "test_all_cores_core-mask sub-test validates that the Master lcore
> becomes ready, the test assumes this to be core 1, this is not correct for all
> architectures or all configurations. For example this test will fail on x86_64
> with bypass_core0=False and on Power9 with most smt configurations. This
> patch determines the first (lowest numbered) core from the list of available
> cores and tests that that core becomes ready.
>
> I validated this change that the test will pass on both Power9 and
> x86_64 with both true and false setting of bypass_core0.o
>
> Signed-off-by: David Wilder <dwilder@us.ibm.com>
> ---
> tests/TestSuite_coremask.py | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/tests/TestSuite_coremask.py b/tests/TestSuite_coremask.py index
> 921dc31..7299e0c 100644
> --- a/tests/TestSuite_coremask.py
> +++ b/tests/TestSuite_coremask.py
> @@ -92,14 +92,16 @@ class TestCoremask(TestCase):
>
> core_mask = utils.create_mask(self.all_cores[:available_max_lcore - 1])
>
> + first_core=self.all_cores[0]
> +
> command = command_line % (self.target, core_mask,
> self.mem_channel)
>
> out = self.dut.send_expect(command, "RTE>>", 10)
> - self.verify("EAL: Master lcore 1 is ready" in out,
> - "Core 1 not ready")
> + self.verify("EAL: Master lcore %s is ready" % first_core in out,
> + "Core %s not ready" % first_core )
>
> - self.verify("EAL: Detected lcore 1 as core" in out,
> - "Core 1 not detected")
> + self.verify("EAL: Detected lcore %s as core" % first_core in out,
> + "Core %s not detected" % first_core )
>
> for core in self.all_cores[1:available_max_lcore - 1]:
> self.verify("EAL: lcore %s is ready" % core in out,
> --
> 1.8.3.1
prev parent reply other threads:[~2019-04-15 22:35 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-27 21:21 David Wilder
2019-04-15 22:35 ` Tu, Lijuan [this message]
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