From: "Mo, YufengX" <yufengx.mo@intel.com>
To: "dts@dpdk.org" <dts@dpdk.org>,
"Chen, Zhaoyan" <zhaoyan.chen@intel.com>,
"Tu, Lijuan" <lijuan.tu@intel.com>
Subject: Re: [dts] [PATCH V1 1/1] [next]dts/pktgen: add support pci address mapping sytle
Date: Mon, 23 Sep 2019 06:57:33 +0000 [thread overview]
Message-ID: <B8B15C44A3F2C044966E545C7B7371153E84BA46@shsmsx102.ccr.corp.intel.com> (raw)
In-Reply-To: <20190923065138.8343-2-yufengx.mo@intel.com>
Tested by Mo, YufengX <yufengx.mo@intel.com>
> -----Original Message-----
> From: Mo, YufengX
> Sent: Monday, September 23, 2019 2:52 PM
> To: dts@dpdk.org; Chen, Zhaoyan <zhaoyan.chen@intel.com>; Tu, Lijuan <lijuan.tu@intel.com>
> Cc: Mo, YufengX <yufengx.mo@intel.com>
> Subject: [dts][PATCH V1 1/1] [next]dts/pktgen: add support pci address mapping sytle
>
>
> make pktgen trex port mapping to be compatible with pci address mapping sytle.
>
> Signed-off-by: yufengmx <yufengx.mo@intel.com>
> ---
> framework/dut.py | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/framework/dut.py b/framework/dut.py
> index fc4a2e6..c2ed0f1 100644
> --- a/framework/dut.py
> +++ b/framework/dut.py
> @@ -986,7 +986,8 @@ class Dut(Crb):
> if peer is not None:
> for remotePort in range(len(self.tester.ports_info)):
> if self.tester.ports_info[remotePort]['type'].lower() == 'trex':
> - if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower():
> + if self.tester.ports_info[remotePort]['intf'].lower() == peer.lower() or \
> + self.tester.ports_info[remotePort]['pci'].lower() == peer.lower():
> hits[remotePort] = True
> self.ports_map[dutPort] = remotePort
> break
> --
> 2.21.0
prev parent reply other threads:[~2019-09-23 6:57 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-23 6:51 [dts] [PATCH V1 0/1] " yufengmx
2019-09-23 6:51 ` [dts] [PATCH V1 1/1] " yufengmx
2019-09-23 6:57 ` Mo, YufengX [this message]
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