From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D72F245DBA; Wed, 27 Nov 2024 21:24:20 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CC738402AE; Wed, 27 Nov 2024 21:24:20 +0100 (CET) Received: from mail-pj1-f51.google.com (mail-pj1-f51.google.com [209.85.216.51]) by mails.dpdk.org (Postfix) with ESMTP id 3B306402AE for ; Wed, 27 Nov 2024 21:24:18 +0100 (CET) Received: by mail-pj1-f51.google.com with SMTP id 98e67ed59e1d1-2ea2dd09971so137049a91.3 for ; Wed, 27 Nov 2024 12:24:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iol.unh.edu; s=unh-iol; t=1732739057; x=1733343857; darn=dpdk.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=qnCd7kWgXG0eNEHG+ThyulsTJ55zoNbmt0gRPEYodcY=; b=Nsa9KqyCHKWlmu3dqsyNIQ5whDvejONUVT1EJl3PEJypJIkKqufwtRYAXYtPIEozRT fH11kzNEIUBha52+kJy9EXbtqflZqmv/l4ZoS/wGcuwkxeZlYcIRoMXslIlFsNfGz5yF AVL4UIXcWc7Xrd2y/r1Sk53ylSRmF1sPcabLg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1732739057; x=1733343857; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qnCd7kWgXG0eNEHG+ThyulsTJ55zoNbmt0gRPEYodcY=; b=ghSwyVsQcaNT+vc31CLVOvHKd0BiVOtaj/QsjLyHD0HgVqDgMhsW+CdfmzUXOBZd3Q odZuPe2V+FaihFgDNPN4NSj0QXCJ+VUK5SP/pIT4kdXy82PGNEIN/O/Q4LMlmjF1gzsY 1bol3nF0ZmJlSV+U8IBQEfhuArwsSe6jO2wHLE+RnJKsl0lh+ULN2covmTc3aph9efdm RXwpp1YFxVqn5H6irKy+pqkfDxKv28aGPmvRgQV9NmvbUun5KXZTwgSNDngrCglGNrx4 4y1js3fy5Y30UD3z1Po6as0iynlnGAO/5SKGzsg+HuV6jkA+IDZN6gysuImUmd05yB5u PTjA== X-Forwarded-Encrypted: i=1; AJvYcCU94MZiOjg0R4GsO5LI+ERaNGrW7JfeqAenViLwVxTuk11VdwaOwwV81KStYRoHLuVaQoQ=@dpdk.org X-Gm-Message-State: AOJu0YwK4F8Oka335A98zvEpT+hJ7HnjDr3WmTm75FX8TjZgooXbMKt7 B5CvpZ1dE0MSNCGL4+HoYOtUMlQ/yhqCjIsT1oQuMq5tPBSYm35B2cR0aZzH5DC8pNKcAVlQUwO jbrn2i02O8O/gJbPaKEjnSDFseIt3jNENP2erYg== X-Gm-Gg: ASbGncsSxN+0z42Khl9kKxxr1dJFbKifF1M1sYxu/Jbt/XN2ubY3mYslHnAdTW2BVyv lVkOkgSrwAn4vIj3IKkNB7b6WT9o2VektycreO+N3YLsGMUaZjrnG2zZEdss9o1jP X-Google-Smtp-Source: AGHT+IE7qlE/VveF5IE97JkmznBRZjOUGA4IZbZT6ct4/G7JToaAIl2Kpazw7Jgf+9pl6UkvGhfyA0gTQfn1OGl8w4Y= X-Received: by 2002:a17:90b:380c:b0:2ea:5dcf:6f74 with SMTP id 98e67ed59e1d1-2ee08e9d449mr5512359a91.3.1732739057078; Wed, 27 Nov 2024 12:24:17 -0800 (PST) MIME-Version: 1.0 References: <20241030164419.3164992-1-gpalanethra@marvell.com> In-Reply-To: From: Patrick Robb Date: Wed, 27 Nov 2024 15:22:09 -0500 Message-ID: Subject: Re: [EXTERNAL] Re: [PATCH 1/1] Cn10K crypto Tests: Added Marvell Cn10K specific crypto Tests to TestCryptoPerfCryptodevPerf To: Gnanesh Kambalu Palanethra Cc: Cody Cheng , "dts@dpdk.org" , JogaRao Nartu , Bharath Rajendra , Hiral Shah , Jerin Jacob Content-Type: multipart/alternative; boundary="000000000000fc77a90627eabfa2" X-BeenThere: dts@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: test suite reviews and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dts-bounces@dpdk.org --000000000000fc77a90627eabfa2 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Quick update: Cody tried the cross compile workflow but ended up getting the same behavior as he describes in his most recent email, so perhaps this is unrelated to native vs cross compile. We will have to re-assess next week, as we will be out of office tomorrow and Friday for Thanksgiving. But, we will try to be in touch quickly. Thanks, Patrick On Wed, Nov 27, 2024 at 1:01=E2=80=AFPM Patrick Robb wr= ote: > Hi Gnanesh, > > Right, CN10K is a single socket system. I was unsure of why you suggested > --socket-mem 2048 from this though. > > I understand that --socket-mem 2048,0 (what is in your patch) should > allocate 2048 for socket 0 (the only socket) and 0 for socket 1 > (non-existent). Are you suggesting that Cody try using the cryptodevs usi= ng > --socket-mem 2048 instead of --socket-mem 2048,0? We can do so, I just fe= ar > I am misunderstanding what you are getting at. > > As far as build procedure goes, I guess I would expect that we end up wit= h > a good application from cross compile (your workflow) and native compile = on > the CN10K DUT (our workflow). If a CN10K native compile is broken for the > cryptodev application, I'm not sure the patch can be merged under those > conditions. At a minimum this cross compile requirement would have to be > documented in the test procedure. > > Thanks, > Patrick > > On Tue, Nov 26, 2024 at 12:06=E2=80=AFPM Gnanesh Kambalu Palanethra < > gpalanethra@marvell.com> wrote: > >> Hi Cody, >> >> Cn10k uses single socket only. *--socket-mem 2048 *should be >> sufficient. >> >> We are cross compiling the DPDK sources [DPDK-24.7] on an x86 machine >> using marvel toolchain and then placing the application >> (arm64-cn10k-linux-gcc) folder in dut. >> >> I suspect a difference in the compiled application that we are using, du= e >> to the difference in compilation procedure. >> >> Regards, >> Gnanesh >> ------------------------------ >> *From:* Cody Cheng >> *Sent:* Tuesday, November 26, 2024 5:37 AM >> *To:* Gnanesh Kambalu Palanethra >> *Cc:* Patrick Robb ; dts@dpdk.org ; >> JogaRao Nartu ; Bharath Rajendra < >> brajendra@marvell.com>; Hiral Shah ; Jerin Jacob < >> jerinj@marvell.com> >> *Subject:* Re: [EXTERNAL] Re: [PATCH 1/1] Cn10K crypto Tests: Added >> Marvell Cn10K specific crypto Tests to TestCryptoPerfCryptodevPerf >> >> Prioritize security for external emails: >> Confirm sender and content safety before clicking links or opening >> attachments >> Report Suspicious >> >> >> >> Hey Gnanesh, >> >> I'm currently attempting to run the new test cases on our CN10K board, >> but I am encountering a few issues that I need help resolving. >> >> For setup, I created a VF and bound it with the following commands: >> >> echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs >> ./usertools/dpdk-devbind.py -u 0002:20:00.1 >> ./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1 >> >> When I run dts, I am getting the error below: >> >> >> 18/11/2024 17:51:03 dut.172.18.0.254: >> arm64-native-linuxapp-gcc/app/dpdk-test-crypto-perf -l 9,10 -a >> 0002:20:00.1 --socket-mem 2048,0 -n 2 -- --ptest throughput --silent >> True --pool-sz 16384 --total-ops 1000000 --burst-sz 32 --buffer-sz 64 >> --devtype crypto_cn10k --optype auth-then-cipher --cipher-algo >> snow3g-uea2 --cipher-op encrypt --cipher-key-sz 16 --cipher-iv-sz 16 >> --auth-algo aes-cmac --auth-op generate --auth-key-sz 16 --aead-iv-sz >> 0 --digest-sz 4 --csv-friendly True >> 18/11/2024 17:51:04 dut.172.18.0.254: EAL: Detected >> C/resultPU lcores: 24^M >> EAL: Detected NUMA nodes: 1^M >> EAL: Detected static linkage of DPDK^M >> EAL: Multi-process socket /var/run/dpdk/rte/mp_socket^M >> EAL: Selected IOVA mode 'VA'^M >> EAL: VFIO support initialized^M >> EAL: Using IOMMU type 1 (Type 1)^M >> CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM)^M >> CRYPTODEV: Creating cryptodev 0002:20:00.1^M >> CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id: >> 0, max queue pairs: 0^M >> CNXK: dev_init():1560 Failed to validate LMT line^M >> CNXK: roc_cpt_dev_init():763 Failed to init roc device^M >> CNXK: cn10k_cpt_pci_probe():80 Failed to initialize roc cpt rc=3D-14^M >> CRYPTODEV: Closing crypto device 0002:20:00.1^M >> CNXK: cn10k_cpt_pci_probe():116 Could not create device (vendor_id: >> 0x177d device_id: 0xa0f3)^M >> PCI_BUS: Requested device 0002:20:00.1 cannot be used^M >> EAL: Bus (pci) probe failed.^M >> No crypto devices type crypto_cn10k available^M >> USER1: Failed to initialise requested crypto device type^M >> >> >> I observed that if I modify the DPDK build process by adding >> `-Dmax_lcores=3D24` to the meson arguments, the initial error >> disappears. Unfortunately, this introduces a new issue: >> >> >> TestCryptoPerfCryptodevPerf: Test Case >> test_mrvl_chacha20_poly1305_aead Result FAILED: TIMEOUT on >> arm64-native-linuxapp-gcc/app/dpdk-test-crypto-perf -l 1,2 -a >> 0002:20:00.1 --socket-mem 2048,0 -n 2 -- --ptest throughput --silent >> True --pool-sz 16384 --total-ops 10000000 --burst-sz 32 --buffer-sz >> 64,128,256,512,1024,2048 --devtype crypto_cn10k --optype aead >> --aead-algo chacha20-poly1305 --aead-op encrypt --aead-key-sz 32 >> --aead-iv-sz 12 --aead-aad-sz 32 --digest-sz 16 --csv-friendly True >> >/tmp/test_mrvl_chacha20_poly1305_aead.txt >> TestCryptoPerfCryptodevPerf: EAL: Detected CPU lcores: 24 >> EAL: Detected NUMA nodes: 1 >> EAL: Detected static linkage of DPDK >> EAL: Multi-process socket /var/run/dpdk/rte/mp_socket >> EAL: Selected IOVA mode 'VA' >> EAL: VFIO support initialized >> EAL: Using IOMMU type 1 (Type 1) >> CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM) >> CRYPTODEV: Creating cryptodev 0002:20:00.1 >> CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id: >> 0, max queue pairs: 0 >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x42 pf=3D31, vf=3D0 >> CNXK: CPT_LF_Q_BASE: 000000019fbd5400 >> CNXK: CPT_LF_Q_SIZE: 000000000000003d >> CNXK: CPT_LF_Q_INST_PTR: 0000006200000062 >> CNXK: CPT_LF_Q_GRP_PTR: 0000000100000001 >> CNXK: CPT_LF_CTL: 0000000000000052 >> CNXK: CPT_LF_MISC_INT_ENA_W1S: 000000000000006e >> CNXK: CPT_LF_MISC_INT: 0000000000000042 >> CNXK: CPT_LF_INPROG: 0000100080010000 >> CNXK: Count registers for CPT LF0: >> CNXK: Encrypted byte count: 0 >> CNXK: Encrypted packet count: 0 >> CNXK: Decrypted byte count: 0 >> CNXK: Decrypted packet count: 0 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0 >> CNXK: CPT_LF_Q_BASE: 000000019fbd5400 >> CNXK: CPT_LF_Q_SIZE: 000000000000003d >> CNXK: CPT_LF_Q_INST_PTR: 0000006200000062 >> CNXK: CPT_LF_Q_GRP_PTR: 0000000100000001 >> CNXK: CPT_LF_CTL: 0000000000000052 >> CNXK: CPT_LF_MISC_INT_ENA_W1S: 000000000000006e >> CNXK: CPT_LF_MISC_INT: 0000000000000002 >> CNXK: CPT_LF_INPROG: 0000100080010000 >> CNXK: Count registers for CPT LF0: >> CNXK: Encrypted byte count: 0 >> CNXK: Encrypted packet count: 0 >> CNXK: Decrypted byte count: 0 >> CNXK: Decrypted packet count: 0 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2 >> CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA faul= t >> CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0 >> CNXK: CPT_LF_Q_BASE: 000000019fbd5400 >> CNXK: CPT_LF_Q_SIZE: 000000000000003d >> CNXK: CPT_LF_Q_INST_PTR: 0000006200000062 >> CNXK: CPT_LF_Q_GRP_PTR: 0000000100000001 >> CNXK: CPT_LF_CTL: 0000000000000052 >> CNXK: CPT_LF_MISC_INT_ENA_W1S: 000000000000006e >> CNXK: CPT_LF_MISC_INT: 0000000000000002 >> CNXK: CPT_LF_INPROG: 0000100080010000 >> CNXK: Count registers for CPT LF0: >> CNXK: Encrypted byte count: 0 >> CNXK: Encrypted packet count: 0 >> CNXK: Decrypted byte count: 0 >> CNXK: Decrypted packet count: 0 >> CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0 >> CNXK: CPT_LF_Q_BASE: 000000019fbd5400 >> CNXK: CPT_LF_Q_SIZE: 000000000000003d >> CNXK: CPT_LF_Q_INST_PTR: 0000006200000062 >> CNXK: CPT_LF_Q_GRP_PTR: 0000000100000001 >> CNXK: CPT_LF_CTL: 0000000000000052 >> CNXK: CPT_LF_MISC_INT_ENA_W1S: 000000000000006e >> CNXK: CPT_LF_MISC_INT: 0000000000000002 >> CNXK: CPT_LF_INPROG: 0000100080010000 >> CNXK: Count registers for CPT LF0: >> CNXK: Encrypted byte count: 0 >> CNXK: Encrypted packet count: 0 >> CNXK: Decrypted byte count: 0 >> CNXK: Decrypted packet count: 0 >> CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0 >> CNXK: CPT_LF_Q_BASE: 000000019fbd5400 >> CNXK: CPT_LF_Q_SIZE: 000000000000003d >> CNXK: CPT_LF_Q_INST_PTR: 0000006200000062 >> CNXK: CPT_LF_Q_GRP_PTR: 0000000100000001 >> CNXK: CPT_LF_CTL: 0000000000000052 >> CNXK: CPT_LF_MISC_INT_ENA_W1S: 000000000000006e >> CNXK: CPT_LF_MISC_INT: 0000000000000002 >> CNXK: CPT_LF_INPROG: 0000100080010000 >> CNXK: Count registers for CPT LF0: >> CNXK: Encrypted byte count: 0 >> CNXK: Encrypted packet count: 0 >> CNXK: Decrypted byte count: 0 >> CNXK: Decrypted packet count: 0 >> CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0 >> CNXK: CPT_LF_Q_BASE: 000000019fbd5400 >> CNXK: CPT_LF_Q_SIZE: 000000000000003d >> CNXK: CPT_LF_Q_INST_PTR: 0000006200000062 >> CNXK: CPT_LF_Q_GRP_PTR: 0000000100000001 >> CNXK: CPT_LF_CTL: 0000000000000052 >> CNXK: CPT_LF_MISC_INT_ENA_W1S: 000000000000006e >> CNXK: CPT_LF_MISC_INT: 0000000000000002 >> CNXK: CPT_LF_INPROG: 0000100080010000 >> CNXK: Count registers for CPT LF0: >> CNXK: Encrypted byte count: 0 >> CNXK: Encrypted packet count: 0 >> CNXK: Decrypted byte count: 0 >> CNXK: Decrypted packet count: 0 >> CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0 >> CNXK: CPT_LF_Q_BASE: 000000019fbd5400 >> CNXK: CPT_LF_Q_SIZE: 000000000000003d >> CNXK: CPT_LF_Q_INST_PTR: 0000006200000062 >> CNXK: CPT_LF_Q_GRP_PTR: 0000000100000001 >> CNXK: CPT_LF_CTL: 0000000000000052 >> CNXK: CPT_LF_MISC_INT_ENA_W1S: 000000000000006e >> CNXK: CPT_LF_MISC_INT: 0000000000000002 >> CNXK: CPT_LF_INPROG: 0000100080010000 >> CNXK: Count registers for CPT LF0: >> CNXK: Encrypted byte count: 0 >> CNXK: Encrypted packet count: 0 >> CNXK: Decrypted byte count: 0 >> CNXK: Decrypted packet count: 0 >> CNXK: cn10k_cpt_dequeue_burst():1325 Request timed out >> CNXK: Lcore ID: 2, LF/QP ID: 0 >> CNXK: >> CNXK: S/w pending queue: >> CNXK: Head: 95 >> CNXK: Tail: 96 >> CNXK: Mask: 0x7ff >> CNXK: Inflight count: 2047 >> CNXK: >> CNXK: H/w pending queue: >> CNXK: Inflight in engines: 0 >> CNXK: NQ ptr: 0x62 >> CNXK: DQ ptr: 0x62 >> CNXK: Insts waiting in CPT: 0 >> CNXK: >> CNXK: CPT AF registers: >> CNXK: CPT_AF_LF0_CTL: 0x0007000000040001 >> CNXK: CPT_AF_LF0_CTL2: 0x0000000000000002 >> CNXK: inst_req_pc: 0x0000000000000163 >> CNXK: inst_lat_pc: 0x00000000002e1a2e >> CNXK: rd_req_pc: 0x0000000000001641 >> CNXK: rd_lat_pc: 0x00000000001146b4 >> CNXK: rd_uc_pc: 0x0000000000000fd0 >> CNXK: active_cycles_pc: 0x0000000000f978e3 >> CNXK: ctx_mis_pc: 0x0000000000000005 >> CNXK: ctx_hit_pc: 0x000000000000015b >> CNXK: ctx_aop_pc: 0x0000000000000000 >> CNXK: ctx_aop_lat_pc: 0x0000000000000000 >> CNXK: ctx_ifetch_pc: 0x000000000000000a >> CNXK: ctx_ifetch_lat_pc: 0x00000000000009be >> CNXK: ctx_ffetch_pc: 0x0000000000000160 >> CNXK: ctx_ffetch_lat_pc: 0x0000000000000992 >> CNXK: ctx_wback_pc: 0x0000000000000160 >> CNXK: ctx_wback_lat_pc: 0x0000000000000992 >> CNXK: ctx_psh_pc: 0x0000000000000160 >> CNXK: ctx_psh_lat_pc: 0x0000000000000992 >> CNXK: ctx_err: 0x0000000000000000 >> CNXK: ctx_enc_id: 0x0000000000000000 >> CNXK: ctx_flush_timer: 0x000000000002faf0 >> CNXK: rxc_time: 0x000000000003873a >> CNXK: rxc_time_cfg: 0x0000000000000000 >> CNXK: rxc_active_sts: 0x0000000000000000 >> CNXK: rxc_zombie_sts: 0x0000000000000000 >> CNXK: rxc_dfrg: 0x0000000000000000 >> CNXK: x2p_link_cfg0: 0x0000000000040000 >> CNXK: x2p_link_cfg1: 0x0000000000040000 >> CNXK: busy_sts_ae: 0x0000000000000000 >> CNXK: free_sts_ae: 0x0000000000ffffff >> CNXK: busy_sts_se: 0x0000000000000000 >> CNXK: free_sts_se: 0xffffffffffffffff >> CNXK: busy_sts_ie: 0x0000000000000000 >> CNXK: free_sts_ie: 0x00ffffffffffffff >> CNXK: exe_err_info: 0x0000000000000000 >> CNXK: cptclk_cnt: 0x000000169fa8634c >> CNXK: diag: 0x00000000010000ff >> CNXK: cn10k_cpt_dequeue_burst():1325 Request timed out >> CNXK: Lcore ID: 2, LF/QP ID: 0 >> CNXK: >> CNXK: S/w pending queue: >> CNXK: Head: 95 >> CNXK: Tail: 96 >> CNXK: Mask: 0x7ff >> CNXK: Inflight count: 2047 >> CNXK: >> CNXK: H/w pending queue: >> CNXK: Inflight in engines: 0 >> CNXK: NQ ptr: 0x62 >> CNXK: DQ ptr: 0x62 >> CNXK: Insts waiting in CPT: 0 >> CNXK: >> CNXK: CPT AF registers: >> CNXK: CPT_AF_LF0_CTL: 0x0007000000040001 >> CNXK: CPT_AF_LF0_CTL2: 0x0000000000000002 >> CNXK: inst_req_pc: 0x0000000000000163 >> CNXK: inst_lat_pc: 0x00000000002e1a2e >> CNXK: rd_req_pc: 0x0000000000001641 >> CNXK: rd_lat_pc: 0x00000000001146b4 >> CNXK: rd_uc_pc: 0x0000000000000fd0 >> CNXK: active_cycles_pc: 0x0000000000f9b66c >> CNXK: ctx_mis_pc: 0x0000000000000005 >> CNXK: ctx_hit_pc: 0x000000000000015b >> CNXK: ctx_aop_pc: 0x0000000000000000 >> CNXK: ctx_aop_lat_pc: 0x0000000000000000 >> CNXK: ctx_ifetch_pc: 0x000000000000000a >> CNXK: ctx_ifetch_lat_pc: 0x00000000000009be >> CNXK: ctx_ffetch_pc: 0x0000000000000160 >> CNXK: ctx_ffetch_lat_pc: 0x0000000000000992 >> CNXK: ctx_wback_pc: 0x0000000000000160 >> CNXK: ctx_wback_lat_pc: 0x0000000000000992 >> CNXK: ctx_psh_pc: 0x0000000000000160 >> CNXK: ctx_psh_lat_pc: 0x0000000000000992 >> CNXK: ctx_err: 0x0000000000000000 >> CNXK: ctx_enc_id: 0x0000000000000000 >> CNXK: ctx_flush_timer: 0x000000000002faf0 >> CNXK: rxc_time: 0x0000000000009ce5 >> CNXK: rxc_time_cfg: 0x0000000000000000 >> CNXK: rxc_active_sts: 0x0000000000000000 >> CNXK: rxc_zombie_sts: 0x0000000000000000 >> CNXK: rxc_dfrg: 0x0000000000000000 >> CNXK: x2p_link_cfg0: 0x0000000000040000 >> CNXK: x2p_link_cfg1: 0x0000000000040000 >> CNXK: busy_sts_ae: 0x0000000000000000 >> CNXK: free_sts_ae: 0x0000000000ffffff >> CNXK: busy_sts_se: 0x0000000000000000 >> CNXK: free_sts_se: 0xffffffffffffffff >> CNXK: busy_sts_ie: 0x0000000000000000 >> CNXK: free_sts_ie: 0x00ffffffffffffff >> CNXK: exe_err_info: 0x0000000000000000 >> CNXK: cptclk_cnt: 0x00000016a6eb1638 >> CNXK: diag: 0x00000000010000ff >> CNXK: cn10k_cpt_dequeue_burst():1325 Request timed out >> CNXK: Lcore ID: 2, LF/QP ID: 0 >> >> This `cn10k_cpt_dequeue_burst():1325 Request timed out` error will >> keep repeating until DTS times out. >> >> Could you please take a look and let me know if there's any >> configuration or additional step that I might have missed to resolve >> these issues? >> I'd be happy to provide more details if needed. >> >> Thank you for your help! >> >> Best Regards, >> Cody Cheng >> >> On Thu, Nov 14, 2024 at 2:23=E2=80=AFPM Gnanesh Kambalu Palanethra >> wrote: >> > >> > >> > Hi Patrick, >> > >> > Please find my responses inline. I am submitting an updated patch ba= sed on your comments. >> > >> > >> > Regards, >> > Gnanesh >> > ________________________________ >> > From: Patrick Robb >> > Sent: Friday, November 1, 2024 3:45 AM >> > To: Gnanesh Kambalu Palanethra >> > Cc: dts@dpdk.org ; JogaRao Nartu ;= Bharath Rajendra ; Cody Cheng ;= Hiral Shah ; Jerin Jacob >> > Subject: [EXTERNAL] Re: [PATCH 1/1] Cn10K crypto Tests: Added Marvell = Cn10K specific crypto Tests to TestCryptoPerfCryptodevPerf >> > >> > Prioritize security for external emails: >> > Confirm sender and content safety before clicking links or opening att= achments >> > Report Suspicious >> > >> > Hi Gnanesh, thanks for sending this. My name is Patrick Robb, and I'm = a CI Testing Lab manager at the DPDK Community Lab hosted at UNH, and a mai= ntainer for the "new" DTS framework which exists within the DPDK repo and s= hould be replacing the legacy DTS project in the long term(what this patch = is for). We do have a Marvell CN10K board at the lab, and I would love to b= egin running some crypto testing from that if possible (so, thanks again fo= r this series). >> > >> > So, most likely we will want to provide a review from UNH and test thi= s, so that it can be merged to DTS (technically I was granted the authority= to apply patches to the legacy repo). >> > >> > I am adding Cody to this thread as I think he can assist me on this. C= ody I am going to provide some comments inline as an initial review for thi= s series, and then we should apply this series locally on the traffic gener= ator/test engine for the CN10K (Intel-1 in our lab), dry run the test which= Gnanesh has added, and report back to him. If all goes well, it should be = possible to merge. >> > >> > Long term, we will want to circle back and add this test to the new DT= S framework, but it is not ready for this test yet, as currently new DTS is= testpmd only - there is not cryptodev support. Although, adding such suppo= rt to new DTS is something I would love to work with you on in the next yea= r if you have time available for development towards DPDK testing! Anyways,= comments inline: >> > >> > On Wed, Oct 30, 2024 at 12:44=E2=80=AFPM Gnanesh wrote: >> > >> > Changes included in this patch: >> > -- New TestCases are added for Cn10K CPT Hardware crypto accelerat= or. >> > -- when Testing newly added Testcases it is found Necessary to mak= e Below Changes >> > 1> tests/cryptodev_common.py >> > --> bind_qat_device function is updated to generate VFs= for the given crypto_dev_id >> > --> added New function bind_mrvl_devices to accept list= of PCI Ids and bind it to vfio_pci driver. >> > 2> framework/crb.py >> > --> updated pci_devices_information_uncached_linux Meth= od to handle additional Nic Speeds for Cavium, >> > as it was restricting only to 1 GIG NIC speed >> > >> > >> > Thanks, I also made this change on our local DTS project for cn10k, bu= t the patch was not submitted to the "legacy DTS" mailing list here as it w= as unmaintained (and still is, to David's point). But, if we can do a revie= w it is good to get these things into mainline. Maybe I can rebase our loca= l patch on yours if there were any other changes, and get feedback for cn10= k specific questions. >> > >> > I have a hard time understanding how this 10G NIC speed requirement go= t added in the first place as it was quite peculiar and confused me for a t= ime as it was dropping the ports list! I'm sure you had a similar experienc= e... :) >> > >> > >> > 3> framework/settings.py >> > --> Changed the default Cavium NIC driver to rvu_nicpf. >> > >> > >> > Thanks, we are also running from this change at the Community Lab. But= , I thought you said above you are creating VFs from the bind_qat_device fu= nction. So, does rvu_nicvf need to be added as well? >> > >> > >> > 4> nics/net_device.py >> > --> added Missing expect object >> > 5> conf/crypto_perf_cryptodev_perf.cfg >> > --> added Marvell Cn10K configs for crypto_perf_cryptod= ev_perf >> > 6> framework/ssh_pexpect.py >> > --> output.replace command's output is not set before r= eturning from get_output_all method >> > hence Unnecessarily returning Prompt along with the= output >> > 7> tests/TestSuite_crypto_perf_cryptodev_perf.py >> > --> added Marvell CN10K Testcases >> > >> > >> > Again we will apply these, give them a run, and report back. >> > >> > >> > Updated Below Private functions >> > 6.1> _run_crypto_perf() --> receives additional KW arg= uments >> > 6.2> _parse_output() ---> Updated to handle Marvell C= n10K app command output >> > 6.3> _run_crypto_perf_throughput() --> receives additi= onal KW arguments >> > >> > >> > >> > I don't see any modifications for the build process. Is there a need t= o include "-Dplatform=3Dcn10k" when setting up the build from meson, or is = the default build fine? >> > >> > right now there is no change to build procedure, we are cross compili= ng DPDK on x86 and copying the application on to DUT. >> > >> > >> > >> > >> > >> > >> > Signed-off-by: Gnanesh >> > --- >> > conf/crypto_perf_cryptodev_perf.cfg | 849 +++++++++++++++++= + >> > framework/crb.py | 6 +- >> > framework/settings.py | 4 +- >> > framework/ssh_pexpect.py | 2 +- >> > nics/net_device.py | 3 + >> > tests/TestSuite_crypto_perf_cryptodev_perf.py | 322 ++++++- >> > tests/cryptodev_common.py | 11 +- >> > 7 files changed, 1172 insertions(+), 25 deletions(-) >> > >> > diff --git a/framework/crb.py b/framework/crb.py >> > index 9e3b0a58..2fe9d147 100644 >> > --- a/framework/crb.py >> > +++ b/framework/crb.py >> > @@ -374,15 +374,15 @@ class Crb(object): >> > pass >> > >> > for i in range(len(match)): >> > - # check if device is cavium and check its linkspeed, appe= nd only if it is 10G >> > + # for cavium supported link speed specfied under linkspee= ds >> > if "177d:" in match[i][1]: >> > - linkspeed =3D "10000" >> > + linkspeeds =3D ["40000", "10000", "25000", "50000", "= 100000"] >> > >> > >> > Honestly I don't understand why we have this condition at all. Other d= evices in DTS do not have this check where the portlinks can be dropped in = crbs.py. What do you think about updating the accepted linkspeeds vs just r= emoving this step entirely? Can we expect additional linkspeeds to be added= for 177d in the future, and have this problem crop up again for a new link= speed, or is this list of speeds "final" for 177d? >> > >> > This check is now completely Removed in the updated patch. >> > >> > >> > >> > nic_linkspeed =3D self.send_expect( >> > "cat /sys/bus/pci/devices/%s/net/*/speed" % match= [i][0], >> > "# ", >> > alt_session=3DTrue, >> > ) >> > - if nic_linkspeed.split()[0] =3D=3D linkspeed: >> > + if nic_linkspeed.split()[0] in linkspeeds: >> > self.pci_devices_info.append((match[i][0], match[= i][1])) >> > else: >> > self.pci_devices_info.append((match[i][0], match[i][1= ])) >> > diff --git a/framework/settings.py b/framework/settings.py >> > index 1a561dda..b2c371f8 100644 >> > --- a/framework/settings.py >> > +++ b/framework/settings.py >> > @@ -166,8 +166,8 @@ DRIVERS =3D { >> > "cavium_a034": "thunder-nicvf", >> > "cavium_0011": "thunder-nicvf", >> > "IXGBE_10G-X550EM_X_SFP": "ixgbe", >> > - "cavium_a063": "octeontx2-nicpf", >> > - "cavium_a064": "octeontx2-nicvf", >> > + "cavium_a063": "rvu_nicpf", >> > + "cavium_a064": "rvu_nicvf", >> > >> > >> > Okay disregard my comment from above about nicvf, I see you've added i= t. Please do update the commit message to reflect that this is included. An= d, while you're at it, you can update the commit message to accord with the= style guidelines for submitting DPDK patches as seen here on sections 9.6 = and 9.7 https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__doc.dpdk.org= _guides_contributing_patches.html&d=3DDwIFaQ&c=3DnKjWec2b6R0mOyPaz7xtfQ&r= =3DUlaoc1LiTkE5RG69cLkMa7P9xGTL0rP6LosuDS8KOe4&m=3DvVns1KNfhQSJf3ilhnQOFPpn= XVYyIzN1csUdc6rFfMlREYfLTRuin-dnxy8CVeSj&s=3DIHrV3dmsSA_rqBs3IDZTGA2ce2WeX5= SjR8lTna-RWYU&e=3D >> > >> > This change message is already part of the commit message. >> > Regarding the style guideline, I have tried to incorporate in the upda= ted patch, please help me in case further changes are needed >> > >> > >> > :) >> > >> > "ICE_100G-E810C_QSFP": "ice", >> > "ICE_25G-E810C_SFP": "ice", >> > "ICE_25G-E823C_QSFP": "ice", >> > diff --git a/framework/ssh_pexpect.py b/framework/ssh_pexpect.py >> > index 2132c066..a96087d2 100644 >> > --- a/framework/ssh_pexpect.py >> > +++ b/framework/ssh_pexpect.py >> > @@ -186,7 +186,7 @@ class SSHPexpect: >> > >> > def get_output_all(self): >> > output =3D self.session.before >> > - output.replace("[PEXPECT]", "") >> > + output =3D output.replace("[PEXPECT]#", "") >> > >> > >> > So, this is just removing the leading "#" from the output? I'm not sur= e we should be making styling changes for a "deprecated" repository. If I l= ook at this example output, from one of the CI runs of this testsuite on a = quickassist card: >> > >> > # Device 1 on lcore 40 >> > >> > # total operations: 30000000 >> > # Buffer size: 1024 >> > # Burst size: 32 >> > # Number of bursts: 937500 >> > # >> > # Total Average Maximum Minimum >> > # enqueued 30000000 32 32 32 >> > # dequeued 30000000 32 32 1 >> > # cycles 91892876610 3063 304625 485 >> > # time [us] 3675715064 122.520 12185.000 19.400 >> > >> > I imagine the DTS maintainers were aware of this and thought it was th= e most clear way to print the logs. I don't think we need to override that = decision now. >> > >> > This is not a styling change. >> > output.replace will not replace the special prompt "[PEXPECT]" directl= y on the variable. >> > output variable needs to be overwritten to have the output strip of th= e prompt [I am overwriting output ] >> > special prompt variable is "[PEXPECT]#", not the "[PEXPECT]". hence ou= tput will have unwanted "#" string. >> > >> > >> > >> > return output >> > >> > def close(self, force=3DFalse): >> > diff --git a/nics/net_device.py b/nics/net_device.py >> > index 0f9c1af4..dd0d0e92 100644 >> > --- a/nics/net_device.py >> > +++ b/nics/net_device.py >> > @@ -43,6 +43,7 @@ class NetDevice(object): >> > if not isinstance(crb, Crb): >> > raise Exception(" Please input the instance of Crb!!!") >> > self.crb =3D crb >> > + self.__send_expect =3D self.crb.send_expect >> > self.domain_id =3D domain_id >> > self.bus_id =3D bus_id >> > self.devfun_id =3D devfun_id >> > @@ -727,6 +728,8 @@ class NetDevice(object): >> > "/sys/bus/pci/devices/%s:%s:%s" % (domain_id, bus_id, dev= fun_id), >> > vf_reg_file, >> > ) >> > + self.__send_expect("echo 0 > %s" % >> > + (vf_reg_path), "# ") >> > >> > >> > So, the pre-existing VFs need to be destroyed before a new set of VFs = can be created? Do you know if this is Marvell specific, or a universal beh= avior? >> > >> > I am not aware of the other boards, but it is the clean way of creatin= g the VFs. >> > >> > >> > self.__send_expect("echo %d > %s" % (int(vf_num), vf_reg_path= ), "# ") >> > >> > def generate_sriov_vfs_linux_igb_uio(self, domain_id, bus_id, dev= fun_id, vf_num): >> > diff --git a/tests/TestSuite_crypto_perf_cryptodev_perf.py b/tests/Tes= tSuite_crypto_perf_cryptodev_perf.py >> > index a3f48eee..b435cefa 100644 >> > --- a/tests/TestSuite_crypto_perf_cryptodev_perf.py >> > +++ b/tests/TestSuite_crypto_perf_cryptodev_perf.py >> > @@ -59,14 +59,74 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > "# ", >> > 5, >> > ) >> > - >> > - cc.bind_qat_device(self, "vfio-pci") >> > + if self.nic =3D=3D "cavium_a063": >> > + count =3D len(self.get_suite_cfg().get('l').split(",")) -= 1 >> > + cc.bind_qat_device(self, "vfio-pci", generate_vfs=3DTrue,= vf_count=3Dcount) >> > + else: >> > + cc.bind_qat_device(self, "vfio-pci") >> > >> > >> > If we are going to use this function for non-QAT devices, can we pleas= e update the function name to prevent confusion? It looks like it's a short= list: >> > >> > Addressed this in the updated patch >> > >> > probb@d121003:~/repos/dts> grep -r "bind_qat_d" . >> > ./tests/TestSuite_compressdev_qat_pmd.py: cc.bind_qat_device(se= lf, self.drivername) >> > ./tests/TestSuite_crypto_perf_cryptodev_perf.py: cc.bind_qat_de= vice(self, "vfio-pci") >> > ./tests/TestSuite_fips_cryptodev.py: cc.bind_qat_device(self, "= vfio-pci") >> > ./tests/TestSuite_ipsec_gw_cryptodev_func.py: cc.bind_qat_devic= e(self, self.drivername) >> > ./tests/TestSuite_l2fwd_cryptodev_func.py: cc.bind_qat_device(s= elf, self.drivername) >> > ./tests/TestSuite_virtio_ipsec_cryptodev_func.py: cc.bind_qat_d= evice(self, self.drivername) >> > ./tests/TestSuite_virtio_perf_cryptodev_func.py: cc.bind_qat_de= vice(self, self.drivername) >> > ./tests/TestSuite_virtio_unit_cryptodev_func.py: cc.bind_qat_de= vice(self, self.drivername) >> > ./tests/compress_common.py:def bind_qat_device(test_case, driver=3D"ig= b_uio"): >> > ./tests/cryptodev_common.py:def bind_qat_device(test_case, driver=3D"i= gb_uio"): >> > >> > >> > >> > >> > src_files =3D ["dep/test_aes_cbc.data", "dep/test_aes_gcm.dat= a"] >> > self.dut_file_dir =3D "/tmp" >> > for file in src_files: >> > self.dut.session.copy_file_to(file, self.dut_file_dir) >> > >> > def tear_down_all(self): >> > + if self.nic =3D=3D "cavium_a063": >> > + cc.bind_qat_device(self, "vfio-pci", generate_vfs=3DTrue, >> > + vf_count=3D2) >> > + import pandas as pd >> > >> > >> > I don't have a problem with this, but I'm just wondering why this is i= mported here as opposed to the top of the file? >> > >> > wrt to pandas import, as we are generating this report only in Marvell= case. this import should not affect others >> > >> > >> > + tuples =3D [('TestCase',), ('performance', 'failed_enq'), >> > + ('performance', 'failed_deq'), >> > + ('performance', 'throughput_mops'), >> > + ('performance', 'cycle_buf'), >> > + ('performance', 'throughput', 'value'), >> > + ('performance', 'throughput', 'delta'), >> > + ('parameters', 'core_num/thread_num'), >> > + ('parameters', 'frame_size'), >> > + ('parameters', 'burst_size'), >> > + ('parameters', 'total_ops'), ('status',)] >> > + mindex =3D pd.MultiIndex.from_tuples(tuples) >> > + index =3D 0 >> > + df =3D pd.DataFrame([], columns=3Dmindex) >> > + for tname, data in self._perf_result.items(): >> > + for dt in data: >> > + for key, value in dt.items(): >> > + df.loc[index, 'TestCase'] =3D tname >> > + if key =3D=3D 'status': >> > + df.loc[index, (key)] =3D value >> > + continue >> > + for item in value: >> > + if item['name'] =3D=3D 'throughput': >> > + df.loc[index, (key, item['name'], 'va= lue')] =3D item['value'] >> > + df.loc[index, (key, item['name'], 'de= lta')] =3D item['delta'] >> > + else: >> > + df.loc[index, (key, item['name'])] = =3D item['value'] >> > + index +=3D 1 >> > + perf_xl =3D self.logger.log_path + "/" + "perf_cryptodev_= result.xls" >> > + writer =3D pd.ExcelWriter(perf_xl, engine=3D'xlsxwriter') >> > + wb =3D writer.book >> > + df.to_excel(writer, sheet_name=3D'Sheet1') >> > + ws =3D writer.sheets["Sheet1"] >> > + merge_format =3D wb.add_format({"bold": 1,"border": 1,"al= ign": "center", >> > + "valign": "vcenter"}) >> > + ws.merge_range('B1:B3', "TestCase", merge_format) >> > + ws.merge_range('C2:C3', "failed_enq", merge_format) >> > + ws.merge_range('D2:D3', "failed_deq", merge_format) >> > + ws.merge_range('E2:E3', "throughput_mops", merge_format) >> > + ws.merge_range('F2:F3', "throughput_mops", merge_format) >> > + ws.merge_range('I2:I3', "core_num/thread_num", merge_form= at) >> > + ws.merge_range('J2:J3', "frame_size", merge_format) >> > + ws.merge_range('K2:K3', "burst_size", merge_format) >> > + ws.merge_range('L2:L3', "total_ops", merge_format) >> > + ws.merge_range('M1:M3', "status", merge_format) >> > + >> > + format1 =3D wb.add_format({"bg_color": "#C6EFCE", "font_c= olor": "#006100", "border": 1}) >> > + format2 =3D wb.add_format({"bg_color": "#FFC7CE", "font_c= olor": "#9C0006"}) >> > + ws.conditional_format("B1:M3", {"type": "cell", "criteria= ": ">=3D", "value": 0 , 'format': format2}) >> > + condition =3D 'B5:M%s'%(5+len(df)-1) >> > + ws.conditional_format(condition, {'type': 'no_blanks', 'f= ormat':format1}) >> > + ws.autofit() >> > + >> > + wb.close() >> > if self._perf_result: >> > with open( >> > self.logger.log_path + "/" + "perf_cryptodev_result.j= son", "a" >> > @@ -175,12 +235,197 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > def test_scheduler_zuc(self): >> > self._run_crypto_perf_throughput() >> > >> > + # Marvell CN10K Testcases >> > + def _crypto_func_cn10k(self): >> > + """Functional tests Helper >> > + Returns: >> > + None >> > + """ >> > + self._run_crypto_func() >> > + >> > + def _crypto_perf_cn10k(self): >> > + """Perf tests Helper function >> > + Returns: >> > + None >> > + """ >> > + self._run_crypto_perf_throughput(expected=3D"# ", >> > + trim_whitespace=3DFalse) >> > + def test_perf_mrvl_aes_cbc(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_gcm_encrypt(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_cbc_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_sha2_256_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_zuc_eea3_cipher_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_zuc_eia3_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_gmac_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_null_cipher_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_snow3g_uea2_cipher_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_kasumi_f8_cipher_only(self): >> > + self._crypto_perf_cn10k() #F >> > + >> > + def test_perf_mrvl_snow3g_uia2_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_kasumi_f9_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha1_hmac_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha1_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_ctr_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_ctr_snow_3g_uia2_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_cmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_3des_cbc_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha1_hmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_224_hmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_256_hmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_384_hmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_ctr_snow_3g_uia2_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_ctr_zuc_eia3_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_ctr_aes_cmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_zuc_eea3_snow3g_uia2_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_zuc_eea3_zuc_eia3_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_zuc_eea3_aes_cmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_snow3g_uea2_snow3g_uia2_cipher_then_auth(self)= : >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_snow3g_uea2_zuc_eia3_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_snow3g_uea2_aes_cmac_cipher_then_auth(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_md5_hmac_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_ctr_cipher_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_3des_cbc_cipher_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_224_hmac_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_256_hmac_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_384_hmac_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_512_hmac_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_aes_xts__cipher_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_des_cbc_cipher_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_md5_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha512_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha384_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha256_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha224_auth_only(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_snow3g_uea2_snow3g_uia2(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha1_hmac_armv8(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_perf_mrvl_sha2_hmac_armv8(self): >> > + self._crypto_perf_cn10k() >> > + >> > + def test_mrvl_ptest(self): >> > + self._crypto_func_cn10k() >> > + >> > + def test_mrvl_burst(self): >> > + self._crypto_func_cn10k() >> > + >> > + def test_mrvl_devtype(self): >> > + self._crypto_func_cn10k() >> > + >> > + def test_mrvl_crypto_sha1_hmac_armv8(self): >> > + self._crypto_func_cn10k() >> > + >> > + def test_mrvl_chacha20_poly1305_aead(self): >> > + self._crypto_func_cn10k() >> > + >> > + def test_mrvl_crypto_sha2_hmac_armv8(self): >> > + self._crypto_func_cn10k() >> > + >> > + def test_mrvl_buffer(self): >> > + self._crypto_func_cn10k() >> > + >> > # Private functions >> > def _run_crypto_func(self): >> > + """ Runs Crypto functional test. >> > + Returns: >> > + None >> > + """ >> > + >> > if cc.is_test_skip(self): >> > return >> > - >> > - cores =3D ",".join(self.dut.get_core_list("1S/2C/1T")) >> > + core_list =3D self.get_suite_cfg().get('core_list',"1S/2C/1T"= ) >> > + cores =3D ",".join(self.dut.get_core_list(core_list)) >> > config =3D {"l": cores} >> > devices =3D self._get_crypto_device(1) >> > if not devices: >> > @@ -206,12 +451,22 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > >> > out =3D self.dut.send_command( >> > "cat %s/%s.txt" % (self.dut_file_dir, self.running_case),= 30 >> > - ) >> > - >> > + ).strip() >> > self.verify("Error" not in out, "Test function failed") >> > self.verify("failed" not in out, "Test function failed") >> > - >> > - def _run_crypto_perf(self): >> > + assert (out !=3D ""), "No output" >> > + >> > + def _run_crypto_perf(self, **kwargs): >> > + """ Runs Crypto Performance test. >> > + Args: >> > + **kwargs: >> > + expected: send_expect match prompt >> > + trim_whitespace: trime whitespace from command output >> > + Returns: >> > + None >> > + """ >> > + expected =3D kwargs.get("expected", "#") >> > + trim_whitespace =3D kwargs.get("trim_whitespace", True) >> > if cc.is_test_skip(self): >> > return "skip" >> > >> > @@ -222,13 +477,14 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > return "skip" >> > >> > eal_opt_str =3D cc.get_eal_opt_str(self, devices) >> > - crypto_perf_opt_str =3D self._get_crypto_perf_opt_str() >> > + crypto_perf_opt_str =3D self._get_crypto_perf_opt_str(**kwarg= s) >> > >> > cmd_str =3D cc.get_dpdk_app_cmd_str( >> > self._app_path, eal_opt_str, crypto_perf_opt_str >> > ) >> > try: >> > - out =3D self.dut.send_expect(cmd_str, "#", 600) >> > + out =3D self.dut.send_expect(cmd_str, expected, 600, >> > + trim_whitespace=3Dtrim_whitesp= ace) >> > except Exception as ex: >> > self.logger.error(ex) >> > raise ex >> > @@ -237,25 +493,44 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > >> > return results >> > >> > - def _get_crypto_perf_opt_str(self, override_crypto_perf_opts=3D{}= ): >> > + def _get_crypto_perf_opt_str(self, **kwargs): >> > + """get crypto perf app option string >> > + args: >> > + **kwargs: >> > + override_crypto_perf_opts- Suite/Case specfic perf >> > + app config to overwrite defaults >> > + Returns: >> > + crypto perf option string >> > + """ >> > + override_crypto_perf_opts =3D kwargs.get("override_crypto_per= f_opts", {}) >> > return cc.get_opt_str( >> > self, self._default_crypto_perf_opts, override_crypto_per= f_opts >> > ) >> > >> > def _parse_output(self, output): >> > try: >> > + dtype =3D self.get_case_cfg().get('devtype') >> > + match_str =3D r" lcore id|#lcore id" >> > lines =3D output.split("\r\n") >> > line_nb =3D len(lines) >> > self.logger.debug("Total output lines: " + str(line_nb)) >> > >> > for line_index in range(line_nb): >> > - if lines[line_index].startswith(" lcore id"): >> > + if re.match(match_str, lines[line_index]): >> > self.logger.debug("data output line from: " + str= (line_index)) >> > break >> > - data_line =3D line_index - 1 >> > + if dtype =3D=3D 'crypto_cn10k': >> > + data_line =3D line_index + 2 >> > + else: >> > + data_line =3D line_index - 1 >> > + >> > + if len(lines[data_line].split(","))>1: >> > + pattern =3D re.compile(r',') >> > + else: >> > + pattern =3D re.compile(r'\s+') >> > >> > results =3D [] >> > - pattern =3D re.compile(r"\s+") >> > + >> > for line in lines[data_line:-1]: >> > print(line) >> > result =3D {} >> > @@ -334,9 +609,15 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > cpu_info[key] =3D value.strip() >> > core, thread =3D 0, 0 >> > lcores =3D self.get_case_cfg()["l"].split(",") >> > + if 'Core(s) per cluster' in out: >> > + cl_soc1 =3D 'Core(s) per cluster' >> > + cl_soc2 =3D 'Cluster(s)' >> > + else: >> > + cl_soc1 =3D 'Core(s) per socket' >> > + cl_soc2 =3D 'Socket(s)' >> > for lcore in lcores[1:]: >> > - if int(lcore.strip()) < int(cpu_info["Core(s) per socket"= ]) * int( >> > - cpu_info["Socket(s)"] >> > + if int(lcore.strip()) < int(cpu_info[cl_soc1]) * int( >> > + cpu_info[cl_soc2] >> > ): >> > core +=3D 1 >> > thread +=3D 1 >> > @@ -362,6 +643,11 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > dev =3D "crypto_snow3g" >> > elif self.get_case_cfg()["devtype"] =3D=3D "crypto_zuc": >> > dev =3D "crypto_zuc" >> > + elif self.get_case_cfg()["devtype"] =3D=3D "crypto_cn10k": >> > + dev =3D "crypto_cn10k" >> > + vf =3D cc.get_qat_devices(self, cpm_num=3D1, num=3Dnum) >> > + device["a"] =3D ' -a '.join(vf) >> > + device["vdev"] =3D None >> > elif self.get_case_cfg()["devtype"] =3D=3D "crypto_scheduler"= : >> > dev =3D "crypto_scheduler" >> > w =3D cc.get_qat_devices(self, cpm_num=3D3, num=3Dnum * 3= ) >> > @@ -388,8 +674,8 @@ class TestCryptoPerfCryptodevPerf(TestCase): >> > >> > return device >> > >> > - def _run_crypto_perf_throughput(self): >> > - results =3D self._run_crypto_perf() >> > + def _run_crypto_perf_throughput(self, **kwargs): >> > + results =3D self._run_crypto_perf(**kwargs) >> > if results =3D=3D "skip": >> > return >> > self.verify(results, "test results is none, Test Failed") >> > diff --git a/tests/cryptodev_common.py b/tests/cryptodev_common.py >> > index b550b468..91067b05 100644 >> > --- a/tests/cryptodev_common.py >> > +++ b/tests/cryptodev_common.py >> > @@ -8,7 +8,9 @@ from nics.net_device import GetNicObj >> > conf =3D SuiteConf("cryptodev_sample") >> > >> > >> > -def bind_qat_device(test_case, driver=3D"igb_uio"): >> > +def bind_qat_device(test_case, driver=3D"igb_uio", generate_vfs=3DFal= se, >> > + vf_count=3D2, drvr_type=3D'generic'): >> > + >> > if driver =3D=3D "vfio-pci": >> > test_case.dut.send_expect("modprobe vfio", "#", 10) >> > test_case.dut.send_expect("modprobe vfio-pci", "#", 10) >> > @@ -38,6 +40,8 @@ def bind_qat_device(test_case, driver=3D"igb_uio"): >> > devfun_id =3D addr_array[2] >> > pf_port =3D GetNicObj(test_case.dut, domain_id, bus_id, devfu= n_id) >> > >> > + if generate_vfs: >> > + pf_port.generate_sriov_vfs_linux(domain_id, bus_id, devfu= n_id, vf_count, drvr_type) >> > >> > >> > Is this different from calling generate_sriov_vfs(), which I assume is= the "correct" behavior. There appears to be a common practice in legacy DT= S of templating out function names to call instead of using inheritance, so= you will have a base function like bind_port(), and then that templates ou= t calls to bind_port_linux(). bind_port_freebsd(), bind_port_windows() etc.= It's a little strange but it is what it is and we should probably stick wi= th the existing system if we are going to make additions. But, if there is = a practical reason why you did it this way, then okay. :) >> > >> > I missed it initially, addressed it in updated patch. >> > >> > >> > sriov_vfs_pci =3D pf_port.get_sriov_vfs_pci() >> > if not sriov_vfs_pci: >> > raise Exception("can not get vf pci") >> > @@ -51,6 +55,11 @@ def bind_qat_device(test_case, driver=3D"igb_uio"): >> > >> > test_case.dev =3D dev >> > >> > +def bind_mrvl_devices(test_case, driver=3D'vfio-pci', **kwargs): >> > + pci_list =3D kwargs.get("pci_list").split() >> > + for pci in pci_list: >> > + test_case.dut.bind_eventdev_port(driver, pci) >> > + return pci_list >> > >> > def get_qat_devices(test_case, cpm_num=3DNone, num=3D1): >> > if not cpm_num: >> > -- >> > 2.25.1 >> > >> >> --000000000000fc77a90627eabfa2 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Quick update: Cody tried the cross compile workflow but en= ded up getting the same behavior as he describes in his most recent email, = so perhaps this is unrelated to native vs cross compile. We will have to re= -assess next week, as we will be out of office tomorrow and Friday for Than= ksgiving. But, we will try to be in touch quickly.

Thank= s,
Patrick

On Wed, Nov 27, 2024 at 1:0= 1=E2=80=AFPM Patrick Robb <probb@io= l.unh.edu> wrote:
Hi Gnanesh,

Right, CN10K is = a single socket system. I was unsure of why you suggested --socket-mem 2048= from this though.=C2=A0

I understand=C2=A0that --= socket-mem 2048,0 (what is in your patch) should allocate 2048 for socket 0= (the only socket) and 0 for socket 1 (non-existent). Are you suggesting th= at Cody try using the cryptodevs=C2=A0using --socket-mem 2048 instead of --= socket-mem 2048,0? We can do so, I just fear I am misunderstanding what you= are getting at.

As far as build procedure goes, I= guess I would expect that we end up with a good application from cross com= pile (your workflow) and native compile on the CN10K DUT (our workflow). If= a CN10K native compile is broken for the cryptodev application, I'm no= t sure the patch can be merged under those conditions. At a minimum this cr= oss compile requirement would have to be documented in the test procedure.<= /div>

Thanks,=C2=A0
Patrick

On Tue, Nov 2= 6, 2024 at 12:06=E2=80=AFPM Gnanesh Kambalu Palanethra <gpalanethra@marvell.com>= ; wrote:
Hi Cody,=C2=A0

=C2=A0Cn10k uses single socket only.=C2=A0 --socket-mem 2048 should = be sufficient.

We are cross compiling the DPDK sources [DPDK-24.7] on an x86 machine using= marvel toolchain and then placing the application (arm64-cn10k-linux-gcc) = folder in dut.=C2=A0

I suspect a difference in the compiled application that we are using, due t= o the difference in compilation procedure.=C2=A0

Regards,
Gnanesh
From:=C2=A0Cody Cheng <ccheng@iol.unh.edu>=
Sent:=C2=A0Tuesday, November 26, 2024 5:37 AM
To:=C2=A0Gnanesh Kambalu Palanethra <gpalanethra@marvell.com>
Cc:=C2=A0Patrick Robb <probb@iol.unh.edu>; dts@dpdk.org <dts@dpdk.org>; JogaRao Nartu <njogarao@marvell.com>; Bharath Ra= jendra <braje= ndra@marvell.com>; Hiral Shah <hshah@marvell.com>; Jerin Jacob <jerinj@marvell.com>
Subject:=C2=A0Re: [EXTERNAL] Re: [PATCH 1/1] Cn10K crypto Tests: Add= ed Marvell Cn10K specific crypto Tests to TestCryptoPerfCryptodevPerf
=C2=A0
Prioritize security for external emails:
Confirm sender and content safety before clicking links or opening attachme= nts
=C2=A0
Hey Gnanesh=
,

I'm currently attempting to run the new test cases on our CN10K board,
but I am encountering a few issues that I need help resolving.

For setup, I created a VF and bound it with the following commands:

echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs
./usertools/dpdk-devbind.py -u 0002:20:00.1
./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1

When I run dts, I am getting the error below:


18/11/2024 17:51:03 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dut.17=
2.18.0.254:
arm64-native-linuxapp-gcc/app/dpdk-test-crypto-perf =C2=A0-l 9,10 -a
0002:20:00.1 --socket-mem 2048,0 -n 2 =C2=A0-- --ptest throughput --silent
True --pool-sz 16384 --total-ops 1000000 --burst-sz 32 --buffer-sz 64
--devtype crypto_cn10k --optype auth-then-cipher --cipher-algo
snow3g-uea2 --cipher-op encrypt --cipher-key-sz 16 --cipher-iv-sz 16
--auth-algo aes-cmac --auth-op generate --auth-key-sz 16 --aead-iv-sz
0 --digest-sz 4 --csv-friendly True
18/11/2024 17:51:04 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dut.17=
2.18.0.254: EAL: Detected
C/resultPU lcores: 24^M
EAL: Detected NUMA nodes: 1^M
EAL: Detected static linkage of DPDK^M
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket^M
EAL: Selected IOVA mode 'VA'^M
EAL: VFIO support initialized^M
EAL: Using IOMMU type 1 (Type 1)^M
CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM)^M
CRYPTODEV: Creating cryptodev 0002:20:00.1^M
CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id:
0, max queue pairs: 0^M
CNXK: dev_init():1560 Failed to validate LMT line^M
CNXK: roc_cpt_dev_init():763 Failed to init roc device^M
CNXK: cn10k_cpt_pci_probe():80 Failed to initialize roc cpt rc=3D-14^M
CRYPTODEV: Closing crypto device 0002:20:00.1^M
CNXK: cn10k_cpt_pci_probe():116 Could not create device (vendor_id:
0x177d device_id: 0xa0f3)^M
PCI_BUS: Requested device 0002:20:00.1 cannot be used^M
EAL: Bus (pci) probe failed.^M
No crypto devices type crypto_cn10k available^M
USER1: Failed to initialise requested crypto device type^M


I observed that if I modify the DPDK build process by adding
`-Dmax_lcores=3D24` to the meson arguments, the initial error
disappears. Unfortunately, this introduces a new issue:


TestCryptoPerfCryptodevPerf: Test Case
test_mrvl_chacha20_poly1305_aead Result FAILED: TIMEOUT on
arm64-native-linuxapp-gcc/app/dpdk-test-crypto-perf =C2=A0-l 1,2 -a
0002:20:00.1 --socket-mem 2048,0 -n 2 =C2=A0-- --ptest throughput --silent
True --pool-sz 16384 --total-ops 10000000 --burst-sz 32 --buffer-sz
64,128,256,512,1024,2048 --devtype crypto_cn10k --optype aead
--aead-algo chacha20-poly1305 --aead-op encrypt --aead-key-sz 32
--aead-iv-sz 12 --aead-aad-sz 32 --digest-sz 16 --csv-friendly True
>/tmp/test_mrvl_chacha20_poly1305_aead.txt
 =C2=A0 TestCryptoPerfCryptodevPerf: EAL: Detected CPU lcores: 24
EAL: Detected NUMA nodes: 1
EAL: Detected static linkage of DPDK
EAL: Multi-process socket /var/run/dpdk/rte/mp_socket
EAL: Selected IOVA mode 'VA'
EAL: VFIO support initialized
EAL: Using IOMMU type 1 (Type 1)
CNXK: RoC Model: cn10ka_a1 (HW_PLATFORM)
CRYPTODEV: Creating cryptodev 0002:20:00.1
CRYPTODEV: Initialisation parameters - name: 0002:20:00.1,socket id:
0, max queue pairs: 0
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x42 pf=3D31, vf=3D0
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_BASE: 000000019fbd5400
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_SIZE: 000000000000003d
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_INST_PTR: 0000006200000062
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_GRP_PTR: 0000000100000001
CNXK: =C2=A0 =C2=A0 CPT_LF_CTL: 0000000000000052
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT_ENA_W1S: 000000000000006e
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT: 0000000000000042
CNXK: =C2=A0 =C2=A0 CPT_LF_INPROG: 0000100080010000
CNXK: Count registers for CPT LF0:
CNXK: =C2=A0 =C2=A0 Encrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Encrypted packet count: 0
CNXK: =C2=A0 =C2=A0 Decrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Decrypted packet count: 0
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_BASE: 000000019fbd5400
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_SIZE: 000000000000003d
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_INST_PTR: 0000006200000062
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_GRP_PTR: 0000000100000001
CNXK: =C2=A0 =C2=A0 CPT_LF_CTL: 0000000000000052
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT_ENA_W1S: 000000000000006e
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT: 0000000000000002
CNXK: =C2=A0 =C2=A0 CPT_LF_INPROG: 0000100080010000
CNXK: Count registers for CPT LF0:
CNXK: =C2=A0 =C2=A0 Encrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Encrypted packet count: 0
CNXK: =C2=A0 =C2=A0 Decrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Decrypted packet count: 0
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cn10k_cpt_dequeue_post_process():1200 HW completion code 0x2
CNXK: cn10k_cpt_dequeue_post_process():1207 Request failed with DMA fault
CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_BASE: 000000019fbd5400
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_SIZE: 000000000000003d
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_INST_PTR: 0000006200000062
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_GRP_PTR: 0000000100000001
CNXK: =C2=A0 =C2=A0 CPT_LF_CTL: 0000000000000052
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT_ENA_W1S: 000000000000006e
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT: 0000000000000002
CNXK: =C2=A0 =C2=A0 CPT_LF_INPROG: 0000100080010000
CNXK: Count registers for CPT LF0:
CNXK: =C2=A0 =C2=A0 Encrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Encrypted packet count: 0
CNXK: =C2=A0 =C2=A0 Decrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Decrypted packet count: 0
CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_BASE: 000000019fbd5400
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_SIZE: 000000000000003d
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_INST_PTR: 0000006200000062
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_GRP_PTR: 0000000100000001
CNXK: =C2=A0 =C2=A0 CPT_LF_CTL: 0000000000000052
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT_ENA_W1S: 000000000000006e
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT: 0000000000000002
CNXK: =C2=A0 =C2=A0 CPT_LF_INPROG: 0000100080010000
CNXK: Count registers for CPT LF0:
CNXK: =C2=A0 =C2=A0 Encrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Encrypted packet count: 0
CNXK: =C2=A0 =C2=A0 Decrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Decrypted packet count: 0
CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_BASE: 000000019fbd5400
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_SIZE: 000000000000003d
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_INST_PTR: 0000006200000062
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_GRP_PTR: 0000000100000001
CNXK: =C2=A0 =C2=A0 CPT_LF_CTL: 0000000000000052
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT_ENA_W1S: 000000000000006e
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT: 0000000000000002
CNXK: =C2=A0 =C2=A0 CPT_LF_INPROG: 0000100080010000
CNXK: Count registers for CPT LF0:
CNXK: =C2=A0 =C2=A0 Encrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Encrypted packet count: 0
CNXK: =C2=A0 =C2=A0 Decrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Decrypted packet count: 0
CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_BASE: 000000019fbd5400
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_SIZE: 000000000000003d
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_INST_PTR: 0000006200000062
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_GRP_PTR: 0000000100000001
CNXK: =C2=A0 =C2=A0 CPT_LF_CTL: 0000000000000052
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT_ENA_W1S: 000000000000006e
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT: 0000000000000002
CNXK: =C2=A0 =C2=A0 CPT_LF_INPROG: 0000100080010000
CNXK: Count registers for CPT LF0:
CNXK: =C2=A0 =C2=A0 Encrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Encrypted packet count: 0
CNXK: =C2=A0 =C2=A0 Decrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Decrypted packet count: 0
CNXK: cpt_lf_misc_irq():58 Err_irq=3D0x2 pf=3D31, vf=3D0
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_BASE: 000000019fbd5400
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_SIZE: 000000000000003d
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_INST_PTR: 0000006200000062
CNXK: =C2=A0 =C2=A0 CPT_LF_Q_GRP_PTR: 0000000100000001
CNXK: =C2=A0 =C2=A0 CPT_LF_CTL: 0000000000000052
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT_ENA_W1S: 000000000000006e
CNXK: =C2=A0 =C2=A0 CPT_LF_MISC_INT: 0000000000000002
CNXK: =C2=A0 =C2=A0 CPT_LF_INPROG: 0000100080010000
CNXK: Count registers for CPT LF0:
CNXK: =C2=A0 =C2=A0 Encrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Encrypted packet count: 0
CNXK: =C2=A0 =C2=A0 Decrypted byte count: 0
CNXK: =C2=A0 =C2=A0 Decrypted packet count: 0
CNXK: cn10k_cpt_dequeue_burst():1325 Request timed out
CNXK: Lcore ID: 2, LF/QP ID: 0
CNXK:
CNXK: S/w pending queue:
CNXK: Head: 95
CNXK: Tail: 96
CNXK: Mask: 0x7ff
CNXK: Inflight count: 2047
CNXK:
CNXK: H/w pending queue:
CNXK: Inflight in engines: 0
CNXK: NQ ptr: 0x62
CNXK: DQ ptr: 0x62
CNXK: Insts waiting in CPT: 0
CNXK:
CNXK: CPT AF registers:
CNXK: =C2=A0 =C2=A0 CPT_AF_LF0_CTL: 0x0007000000040001
CNXK: =C2=A0 =C2=A0 CPT_AF_LF0_CTL2: 0x0000000000000002
CNXK: =C2=A0 =C2=A0 inst_req_pc: 0x0000000000000163
CNXK: =C2=A0 =C2=A0 inst_lat_pc: 0x00000000002e1a2e
CNXK: =C2=A0 =C2=A0 rd_req_pc: 0x0000000000001641
CNXK: =C2=A0 =C2=A0 rd_lat_pc: 0x00000000001146b4
CNXK: =C2=A0 =C2=A0 rd_uc_pc: 0x0000000000000fd0
CNXK: =C2=A0 =C2=A0 active_cycles_pc: 0x0000000000f978e3
CNXK: =C2=A0 =C2=A0 ctx_mis_pc: 0x0000000000000005
CNXK: =C2=A0 =C2=A0 ctx_hit_pc: 0x000000000000015b
CNXK: =C2=A0 =C2=A0 ctx_aop_pc: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_aop_lat_pc: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_ifetch_pc: 0x000000000000000a
CNXK: =C2=A0 =C2=A0 ctx_ifetch_lat_pc: 0x00000000000009be
CNXK: =C2=A0 =C2=A0 ctx_ffetch_pc: 0x0000000000000160
CNXK: =C2=A0 =C2=A0 ctx_ffetch_lat_pc: 0x0000000000000992
CNXK: =C2=A0 =C2=A0 ctx_wback_pc: 0x0000000000000160
CNXK: =C2=A0 =C2=A0 ctx_wback_lat_pc: 0x0000000000000992
CNXK: =C2=A0 =C2=A0 ctx_psh_pc: 0x0000000000000160
CNXK: =C2=A0 =C2=A0 ctx_psh_lat_pc: 0x0000000000000992
CNXK: =C2=A0 =C2=A0 ctx_err: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_enc_id: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_flush_timer: 0x000000000002faf0
CNXK: =C2=A0 =C2=A0 rxc_time: 0x000000000003873a
CNXK: =C2=A0 =C2=A0 rxc_time_cfg: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 rxc_active_sts: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 rxc_zombie_sts: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 rxc_dfrg: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 x2p_link_cfg0: 0x0000000000040000
CNXK: =C2=A0 =C2=A0 x2p_link_cfg1: 0x0000000000040000
CNXK: =C2=A0 =C2=A0 busy_sts_ae: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 free_sts_ae: 0x0000000000ffffff
CNXK: =C2=A0 =C2=A0 busy_sts_se: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 free_sts_se: 0xffffffffffffffff
CNXK: =C2=A0 =C2=A0 busy_sts_ie: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 free_sts_ie: 0x00ffffffffffffff
CNXK: =C2=A0 =C2=A0 exe_err_info: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 cptclk_cnt: 0x000000169fa8634c
CNXK: =C2=A0 =C2=A0 diag: 0x00000000010000ff
CNXK: cn10k_cpt_dequeue_burst():1325 Request timed out
CNXK: Lcore ID: 2, LF/QP ID: 0
CNXK:
CNXK: S/w pending queue:
CNXK: Head: 95
CNXK: Tail: 96
CNXK: Mask: 0x7ff
CNXK: Inflight count: 2047
CNXK:
CNXK: H/w pending queue:
CNXK: Inflight in engines: 0
CNXK: NQ ptr: 0x62
CNXK: DQ ptr: 0x62
CNXK: Insts waiting in CPT: 0
CNXK:
CNXK: CPT AF registers:
CNXK: =C2=A0 =C2=A0 CPT_AF_LF0_CTL: 0x0007000000040001
CNXK: =C2=A0 =C2=A0 CPT_AF_LF0_CTL2: 0x0000000000000002
CNXK: =C2=A0 =C2=A0 inst_req_pc: 0x0000000000000163
CNXK: =C2=A0 =C2=A0 inst_lat_pc: 0x00000000002e1a2e
CNXK: =C2=A0 =C2=A0 rd_req_pc: 0x0000000000001641
CNXK: =C2=A0 =C2=A0 rd_lat_pc: 0x00000000001146b4
CNXK: =C2=A0 =C2=A0 rd_uc_pc: 0x0000000000000fd0
CNXK: =C2=A0 =C2=A0 active_cycles_pc: 0x0000000000f9b66c
CNXK: =C2=A0 =C2=A0 ctx_mis_pc: 0x0000000000000005
CNXK: =C2=A0 =C2=A0 ctx_hit_pc: 0x000000000000015b
CNXK: =C2=A0 =C2=A0 ctx_aop_pc: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_aop_lat_pc: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_ifetch_pc: 0x000000000000000a
CNXK: =C2=A0 =C2=A0 ctx_ifetch_lat_pc: 0x00000000000009be
CNXK: =C2=A0 =C2=A0 ctx_ffetch_pc: 0x0000000000000160
CNXK: =C2=A0 =C2=A0 ctx_ffetch_lat_pc: 0x0000000000000992
CNXK: =C2=A0 =C2=A0 ctx_wback_pc: 0x0000000000000160
CNXK: =C2=A0 =C2=A0 ctx_wback_lat_pc: 0x0000000000000992
CNXK: =C2=A0 =C2=A0 ctx_psh_pc: 0x0000000000000160
CNXK: =C2=A0 =C2=A0 ctx_psh_lat_pc: 0x0000000000000992
CNXK: =C2=A0 =C2=A0 ctx_err: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_enc_id: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 ctx_flush_timer: 0x000000000002faf0
CNXK: =C2=A0 =C2=A0 rxc_time: 0x0000000000009ce5
CNXK: =C2=A0 =C2=A0 rxc_time_cfg: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 rxc_active_sts: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 rxc_zombie_sts: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 rxc_dfrg: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 x2p_link_cfg0: 0x0000000000040000
CNXK: =C2=A0 =C2=A0 x2p_link_cfg1: 0x0000000000040000
CNXK: =C2=A0 =C2=A0 busy_sts_ae: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 free_sts_ae: 0x0000000000ffffff
CNXK: =C2=A0 =C2=A0 busy_sts_se: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 free_sts_se: 0xffffffffffffffff
CNXK: =C2=A0 =C2=A0 busy_sts_ie: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 free_sts_ie: 0x00ffffffffffffff
CNXK: =C2=A0 =C2=A0 exe_err_info: 0x0000000000000000
CNXK: =C2=A0 =C2=A0 cptclk_cnt: 0x00000016a6eb1638
CNXK: =C2=A0 =C2=A0 diag: 0x00000000010000ff
CNXK: cn10k_cpt_dequeue_burst():1325 Request timed out
CNXK: Lcore ID: 2, LF/QP ID: 0

This `cn10k_cpt_dequeue_burst():1325 Request timed out` error will
keep repeating until DTS times out.

Could you please take a look and let me know if there's any
configuration or additional step that I might have missed to resolve
these issues?
I'd be happy to provide more details if needed.

Thank you for your help!

Best Regards,
Cody Cheng

On Thu, Nov 14, 2024 at 2:23=E2=80=AFPM Gnanesh Kambalu Palanethra
<gpalanethr=
a@marvell.com> wrote:
>
>
> Hi Patrick,
>
> Please find my responses inline.=C2=A0 I am submitting =C2=A0an update=
d patch based on your comments.
>
>
> Regards,
> Gnanesh
> ________________________________
> From: Patrick Robb <probb@iol.unh.edu>
> Sent: Friday, November 1, 2024 3:45 AM
> To: Gnanesh Kambalu Palanethra <gpalanethra@marvell.com>
> Cc: dts@dpdk.org=
 <dts@dpdk.org>=
; JogaRao Nartu <njogarao@marvell.com>; Bharath Rajendra <brajendra@marvell.com>; Cody C=
heng <ccheng@iol=
.unh.edu>; Hiral Shah <hshah@marvell.com>; Jerin Jacob <jerinj@marvell.com>
> Subject: [EXTERNAL] Re: [PATCH 1/1] Cn10K crypto Tests: Added Marvell =
Cn10K specific crypto Tests to TestCryptoPerfCryptodevPerf
>
> Prioritize security for external emails:
> Confirm sender and content safety before clicking links or opening att=
achments
> Report Suspicious
>
> Hi Gnanesh, thanks for sending this. My name is Patrick Robb, and I=
9;m a CI Testing Lab manager at the DPDK Community Lab hosted at UNH, and a=
 maintainer for the "new" DTS framework which exists within the D=
PDK repo and should be replacing the legacy DTS project in the long term(wh=
at this patch is for). We do have a Marvell CN10K board at the lab, and I w=
ould love to begin running some crypto testing from that if possible (so, t=
hanks again for this series).
>
> So, most likely we will want to provide a review from UNH and test thi=
s, so that it can be merged to DTS (technically I was granted the authority=
 to apply patches to the legacy repo).
>
> I am adding Cody to this thread as I think he can assist me on this. C=
ody I am going to provide some comments inline as an initial review for thi=
s series, and then we should apply this series locally on the traffic gener=
ator/test engine for the CN10K (Intel-1 in our lab), dry run the test which=
 Gnanesh has added, and report back to him. If all goes well, it should be =
possible to merge.
>
> Long term, we will want to circle back and add this test to the new DT=
S framework, but it is not ready for this test yet, as currently new DTS is=
 testpmd only - there is not cryptodev support. Although, adding such suppo=
rt to new DTS is something I would love to work with you on in the next yea=
r if you have time available for development towards DPDK testing! Anyways,=
 comments inline:
>
> On Wed, Oct 30, 2024 at 12:44=E2=80=AFPM Gnanesh <gpalanethra@marvell.com>=
 wrote:
>
> =C2=A0 =C2=A0 Changes included in this patch:
> =C2=A0 =C2=A0 -- New TestCases are added for Cn10K CPT Hardware crypto=
 accelerator.
> =C2=A0 =C2=A0 -- when Testing newly added Testcases it is found Necess=
ary to make Below Changes
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 1> tests/cryptodev_common.py
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> bind_qat=
_device function is updated to generate VFs for the given crypto_dev_id
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> added Ne=
w function bind_mrvl_devices to accept list of PCI Ids and bind it to vfio_=
pci driver.
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 2> framework/crb.py
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> updated =
pci_devices_information_uncached_linux Method to handle additional Nic Spee=
ds for Cavium,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0a=
s it was restricting only to 1 GIG NIC speed
>
>
> Thanks, I also made this change on our local DTS project for cn10k, bu=
t the patch was not submitted to the "legacy DTS" mailing list he=
re as it was unmaintained (and still is, to David's point). But, if we =
can do a review it is good to get these things into mainline. Maybe I can r=
ebase our local patch on yours if there were any other changes, and get fee=
dback for cn10k specific questions.
>
> I have a hard time understanding how this 10G NIC speed requirement go=
t added in the first place as it was quite peculiar and confused me for a t=
ime as it was dropping the ports list! I'm sure you had a similar exper=
ience... :)
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 3> framework/settings.py
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> Changed =
the default Cavium NIC driver to rvu_nicpf.
>
>
> Thanks, we are also running from this change at the Community Lab. But=
, I thought you said above you are creating VFs from the bind_qat_device fu=
nction. So, does rvu_nicvf need to be added as well?
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 4> nics/net_device.py
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> added Mi=
ssing expect object
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 5> conf/crypto_perf_cryptodev_pe=
rf.cfg
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> added Ma=
rvell Cn10K configs for crypto_perf_cryptodev_perf
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 6> framework/ssh_pexpect.py
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> output.r=
eplace command's output is not set before returning from get_output_all=
 method
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0h=
ence Unnecessarily returning Prompt along with the output
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 7> tests/TestSuite_crypto_perf_c=
ryptodev_perf.py
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0--> =C2=A0ad=
ded Marvell CN10K Testcases
>
>
> Again we will apply these, give them a run, and report back.
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Updated Below Private =
functions
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 6.1> _run_c=
rypto_perf() --> receives additional KW arguments
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 6.2> _parse=
_output() =C2=A0---> Updated to handle Marvell Cn10K app command output
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 6.3> _run_c=
rypto_perf_throughput() --> receives additional KW arguments
>
>
>
> I don't see any modifications for the build process. Is there a ne=
ed to include "-Dplatform=3Dcn10k" when setting up the build from=
 meson, or is the default build fine?
>
> =C2=A0right now there is no change to build procedure, we are cross co=
mpiling DPDK on x86 and copying the application on to DUT.
>
>
>
>
>
>
> Signed-off-by: Gnanesh <gpalanethra@marvell.com>
> ---
> =C2=A0conf/crypto_perf_cryptodev_perf.cfg =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 | 849 ++++++++++++++++++
> =C2=A0framework/crb.py =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 6 +-
> =C2=A0framework/settings.py =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 4 +-
> =C2=A0framework/ssh_pexpect.py =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 2 +-
> =C2=A0nics/net_device.py =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 3 +
> =C2=A0tests/TestSuite_crypto_perf_cryptodev_perf.py | 322 ++++++-
> =C2=A0tests/cryptodev_common.py =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A011 +-
> =C2=A07 files changed, 1172 insertions(+), 25 deletions(-)
>
> diff --git a/framework/crb.py b/framework/crb.py
> index 9e3b0a58..2fe9d147 100644
> --- a/framework/crb.py
> +++ b/framework/crb.py
> @@ -374,15 +374,15 @@ class Crb(object):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pass
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for i in range(len(match)):
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0# check if device is cavium=
 and check its linkspeed, append only if it is 10G
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0# for cavium supported link=
 speed specfied under linkspeeds
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if "177d:" i=
n match[i][1]:
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0linkspeed =3D=
 "10000"
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0linkspeeds =
=3D ["40000", "10000", "25000", "50000&q=
uot;, "100000"]
>
>
> Honestly I don't understand why we have this condition at all. Oth=
er devices in DTS do not have this check where the portlinks can be dropped=
 in crbs.py. What do you think about updating the accepted linkspeeds vs ju=
st removing this step entirely? Can we expect additional linkspeeds to be a=
dded for 177d in the future, and have this problem crop up again for a new =
linkspeed, or is this list of speeds "final" for 177d?
>
> This check is now completely Removed in the updated patch.
>
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0nic_link=
speed =3D self.send_expect(
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0"cat /sys/bus/pci/devices/%s/net/*/speed" % match[i][0],
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0"# ",
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0alt_session=3DTrue,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if nic_linksp=
eed.split()[0] =3D=3D linkspeed:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if nic_linksp=
eed.split()[0] in =C2=A0linkspeeds:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0self.pci_devices_info.append((match[i][0], match[i][1]))
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0else:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.pci=
_devices_info.append((match[i][0], match[i][1]))
> diff --git a/framework/settings.py b/framework/settings.py
> index 1a561dda..b2c371f8 100644
> --- a/framework/settings.py
> +++ b/framework/settings.py
> @@ -166,8 +166,8 @@ DRIVERS =3D {
> =C2=A0 =C2=A0 =C2=A0"cavium_a034": "thunder-nicvf"=
,
> =C2=A0 =C2=A0 =C2=A0"cavium_0011": "thunder-nicvf"=
,
> =C2=A0 =C2=A0 =C2=A0"IXGBE_10G-X550EM_X_SFP": "ixgbe&qu=
ot;,
> - =C2=A0 =C2=A0"cavium_a063": "octeontx2-nicpf",
> - =C2=A0 =C2=A0"cavium_a064": "octeontx2-nicvf",
> + =C2=A0 =C2=A0"cavium_a063": "rvu_nicpf",
> + =C2=A0 =C2=A0"cavium_a064": "rvu_nicvf",
>
>
> Okay disregard my comment from above about nicvf, I see you've add=
ed it. Please do update the commit message to reflect that this is included=
. And, while you're at it, you can update the commit message to accord =
with the style guidelines for submitting DPDK patches as seen here on secti=
ons 9.6 and 9.7 https://urldefense.proofpoint.com/v2/url?u=3Dhttps-3A__=
doc.dpdk.org_guides_contributing_patches.html&d=3DDwIFaQ&c=3DnKjWec=
2b6R0mOyPaz7xtfQ&r=3DUlaoc1LiTkE5RG69cLkMa7P9xGTL0rP6LosuDS8KOe4&m=
=3DvVns1KNfhQSJf3ilhnQOFPpnXVYyIzN1csUdc6rFfMlREYfLTRuin-dnxy8CVeSj&s=
=3DIHrV3dmsSA_rqBs3IDZTGA2ce2WeX5SjR8lTna-RWYU&e=3D
>
> This change message is already part of the commit message.
> Regarding the style guideline, I have tried to incorporate in the upda=
ted patch, please help me in case further changes are needed
>
>
> :)
>
> =C2=A0 =C2=A0 =C2=A0"ICE_100G-E810C_QSFP": "ice",
> =C2=A0 =C2=A0 =C2=A0"ICE_25G-E810C_SFP": "ice",
> =C2=A0 =C2=A0 =C2=A0"ICE_25G-E823C_QSFP": "ice",
> diff --git a/framework/ssh_pexpect.py b/framework/ssh_pexpect.py
> index 2132c066..a96087d2 100644
> --- a/framework/ssh_pexpect.py
> +++ b/framework/ssh_pexpect.py
> @@ -186,7 +186,7 @@ class SSHPexpect:
>
> =C2=A0 =C2=A0 =C2=A0def get_output_all(self):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0output =3D self.session.before
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0output.replace("[PEXPECT]", &qu=
ot;")
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0output =3D output.replace("[PEXPECT]=
#", "")
>
>
> So, this is just removing the leading "#" from the output? I=
'm not sure we should be making styling changes for a "deprecated&=
quot; repository. If I look at this example output, from one of the CI runs=
 of this testsuite on a quickassist card:
>
> # Device 1 on lcore 40
>
> # total operations: 30000000
> # Buffer size: 1024
> # Burst size: 32
> # =C2=A0 =C2=A0 Number of bursts: 937500
> #
> # =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Total =C2=A0=
 Average =C2=A0 Maximum =C2=A0 Minimum
> # =C2=A0enqueued =C2=A0 =C2=A030000000 =C2=A0 =C2=A0 =C2=A0 =C2=A032 =
=C2=A0 =C2=A0 =C2=A0 =C2=A032 =C2=A0 =C2=A0 =C2=A0 =C2=A032
> # =C2=A0dequeued =C2=A0 =C2=A030000000 =C2=A0 =C2=A0 =C2=A0 =C2=A032 =
=C2=A0 =C2=A0 =C2=A0 =C2=A032 =C2=A0 =C2=A0 =C2=A0 =C2=A0 1
> # =C2=A0 =C2=A0cycles 91892876610 =C2=A0 =C2=A0 =C2=A03063 =C2=A0 =C2=
=A0304625 =C2=A0 =C2=A0 =C2=A0 485
> # time [us] =C2=A03675715064 =C2=A0 122.520 12185.000 =C2=A0 =C2=A019.=
400
>
> I imagine the DTS maintainers were aware of this and thought it was th=
e most clear way to print the logs. I don't think we need to override t=
hat decision now.
>
> This is not a styling change.
> output.replace will not replace the special prompt "[PEXPECT]&quo=
t; directly on the variable.
> output variable needs to be overwritten to have the output strip of th=
e prompt [I am overwriting output ]
> special prompt variable is "[PEXPECT]#", not the "[PEXP=
ECT]". hence output will have unwanted "#" string.
>
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return output
>
> =C2=A0 =C2=A0 =C2=A0def close(self, force=3DFalse):
> diff --git a/nics/net_device.py b/nics/net_device.py
> index 0f9c1af4..dd0d0e92 100644
> --- a/nics/net_device.py
> +++ b/nics/net_device.py
> @@ -43,6 +43,7 @@ class NetDevice(object):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if not isinstance(crb, Crb):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0raise Exception("=
 =C2=A0Please input the instance of Crb!!!")
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.crb =3D crb
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self.__send_expect =3D self.crb.send_expe=
ct
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.domain_id =3D domain_id
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.bus_id =3D bus_id
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.devfun_id =3D devfun_id
> @@ -727,6 +728,8 @@ class NetDevice(object):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"/sys/bus/pci/dev=
ices/%s:%s:%s" % (domain_id, bus_id, devfun_id),
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0vf_reg_file,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self.__send_expect("echo 0 > %s&q=
uot; %
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 (vf_reg_path), "# ")
>
>
> So, the pre-existing VFs need to be destroyed before a new set of VFs =
can be created? Do you know if this is Marvell specific, or a universal beh=
avior?
>
> I am not aware of the other boards, but it is the clean way of creatin=
g the VFs.
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.__send_expect("echo %d >=
; %s" % (int(vf_num), vf_reg_path), "# ")
>
> =C2=A0 =C2=A0 =C2=A0def generate_sriov_vfs_linux_igb_uio(self, domain_=
id, bus_id, devfun_id, vf_num):
> diff --git a/tests/TestSuite_crypto_perf_cryptodev_perf.py b/tests/Tes=
tSuite_crypto_perf_cryptodev_perf.py
> index a3f48eee..b435cefa 100644
> --- a/tests/TestSuite_crypto_perf_cryptodev_perf.py
> +++ b/tests/TestSuite_crypto_perf_cryptodev_perf.py
> @@ -59,14 +59,74 @@ class TestCryptoPerfCryptodevPerf(TestCase):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"# =
",
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A05,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0)
> -
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cc.bind_qat_device(self, "vfio-pci&q=
uot;)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if self.nic =3D=3D "cavium_a063"=
;:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0count =3D len(self.get_suit=
e_cfg().get('l').split(",")) - 1
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cc.bind_qat_device(self, &q=
uot;vfio-pci", generate_vfs=3DTrue, vf_count=3Dcount)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0else:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cc.bind_qat_device(self, &q=
uot;vfio-pci")
>
>
> If we are going to use this function for non-QAT devices, can we pleas=
e update the function name to prevent confusion? It looks like it's a s=
hort list:
>
> Addressed this in =C2=A0the updated patch
>
> probb@d121003:~/repos/dts> grep -r "bind_qat_d" .
> ./tests/TestSuite_compressdev_qat_pmd.py: =C2=A0 =C2=A0 =C2=A0 =C2=A0c=
c.bind_qat_device(self, self.drivername)
> ./tests/TestSuite_crypto_perf_cryptodev_perf.py: =C2=A0 =C2=A0 =C2=A0 =
=C2=A0cc.bind_qat_device(self, "vfio-pci")
> ./tests/TestSuite_fips_cryptodev.py: =C2=A0 =C2=A0 =C2=A0 =C2=A0cc.bin=
d_qat_device(self, "vfio-pci")
> ./tests/TestSuite_ipsec_gw_cryptodev_func.py: =C2=A0 =C2=A0 =C2=A0 =C2=
=A0cc.bind_qat_device(self, self.drivername)
> ./tests/TestSuite_l2fwd_cryptodev_func.py: =C2=A0 =C2=A0 =C2=A0 =C2=A0=
cc.bind_qat_device(self, self.drivername)
> ./tests/TestSuite_virtio_ipsec_cryptodev_func.py: =C2=A0 =C2=A0 =C2=A0=
 =C2=A0cc.bind_qat_device(self, self.drivername)
> ./tests/TestSuite_virtio_perf_cryptodev_func.py: =C2=A0 =C2=A0 =C2=A0 =
=C2=A0cc.bind_qat_device(self, self.drivername)
> ./tests/TestSuite_virtio_unit_cryptodev_func.py: =C2=A0 =C2=A0 =C2=A0 =
=C2=A0cc.bind_qat_device(self, self.drivername)
> ./tests/compress_common.py:def bind_qat_device(test_case, driver=3D&qu=
ot;igb_uio"):
> ./tests/cryptodev_common.py:def bind_qat_device(test_case, driver=3D&q=
uot;igb_uio"):
>
>
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0src_files =3D ["dep/test_aes_cb=
c.data", "dep/test_aes_gcm.data"]
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.dut_file_dir =3D "/tmp&quo=
t;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for file in src_files:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.dut.session.copy_=
file_to(file, self.dut_file_dir)
>
> =C2=A0 =C2=A0 =C2=A0def tear_down_all(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if self.nic =3D=3D "cavium_a063"=
;:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cc.bind_qat_device(self, &q=
uot;vfio-pci", generate_vfs=3DTrue,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 vf_count=3D2)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0import pandas as pd
>
>
> I don't have a problem with this, but I'm just wondering why t=
his is imported here as opposed to the top of the file?
>
> wrt to pandas import, as we are generating this report only in Marvell=
 case. this import should not affect others
>
>
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0tuples =3D [('TestCase&=
#39;,), ('performance', 'failed_enq'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('performance', 'failed_deq'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('performance', 'throughput_mops'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('performance', 'cycle_buf'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('performance', 'throughput', 'value'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('performance', 'throughput', 'delta'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('parameters', 'core_num/thread_num'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('parameters', 'frame_size'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('parameters', 'burst_size'),
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0('parameters', 'total_ops'), ('status',)]
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mindex =3D pd.MultiIndex.fr=
om_tuples(tuples)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0index =3D 0
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0df =3D pd.DataFrame([], col=
umns=3Dmindex)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for tname, data in self._pe=
rf_result.items():
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for dt in dat=
a:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0for key, value in dt.items():
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0df.loc[index, 'TestCase'] =3D tname
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0if key =3D=3D 'status':
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0df.loc[index, (key)] =3D value
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0continue
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0for item in value:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if item['name'] =3D=3D 'throughp=
ut':
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0df.loc[index, (key, item['=
name'], 'value')] =3D item['value']
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0df.loc[index, (key, item['=
name'], 'delta')] =3D item['delta']
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0else:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0df.loc[index, (key, item['=
name'])] =3D item['value']
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0index +=3D 1
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0perf_xl =3D self.logger.log=
_path + "/" + "perf_cryptodev_result.xls"
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0writer =3D pd.ExcelWriter(p=
erf_xl, engine=3D'xlsxwriter')
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0wb =C2=A0=3D writer.book
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0df.to_excel(writer, sheet_n=
ame=3D'Sheet1')
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws =3D writer.sheets["=
Sheet1"]
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0merge_format =3D wb.add_for=
mat({"bold": 1,"border": 1,"align": "cen=
ter",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0"valign": "vcenter"})
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('B1:B3&#=
39;, "TestCase", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('C2:C3&#=
39;, "failed_enq", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('D2:D3&#=
39;, "failed_deq", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('E2:E3&#=
39;, "throughput_mops", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('F2:F3&#=
39;, "throughput_mops", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('I2:I3&#=
39;, "core_num/thread_num", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('J2:J3&#=
39;, "frame_size", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('K2:K3&#=
39;, "burst_size", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('L2:L3&#=
39;, "total_ops", merge_format)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.merge_range('M1:M3&#=
39;, "status", merge_format)
> +
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0format1 =3D wb.add_format({=
"bg_color": "#C6EFCE", "font_color": "#0=
06100", "border": 1})
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0format2 =3D wb.add_format({=
"bg_color": "#FFC7CE", "font_color": "#9=
C0006"})
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.conditional_format("=
;B1:M3", {"type": "cell", "criteria": &q=
uot;>=3D", "value": 0 , 'format': format2})
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0condition =3D 'B5:M%s&#=
39;%(5+len(df)-1)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.conditional_format(condi=
tion, {'type': 'no_blanks', 'format':format1})
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ws.autofit()
> +
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0wb.close()
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if self._perf_result:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0with open(
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.log=
ger.log_path + "/" + "perf_cryptodev_result.json", &quo=
t;a"
> @@ -175,12 +235,197 @@ class TestCryptoPerfCryptodevPerf(TestCase):
> =C2=A0 =C2=A0 =C2=A0def test_scheduler_zuc(self):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self._run_crypto_perf_throughput()
>
> + =C2=A0 =C2=A0# Marvell CN10K Testcases
> + =C2=A0 =C2=A0def _crypto_func_cn10k(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""Functional tests Helper
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0Returns:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 None
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._run_crypto_func()
> +
> + =C2=A0 =C2=A0def _crypto_perf_cn10k(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""Perf tests Helper funct=
ion
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0Returns:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 None
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._run_crypto_perf_throughput(expected=
=3D"# ",
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 t=
rim_whitespace=3DFalse)
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_cbc(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_gcm_encrypt(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_cbc_cipher_then_auth(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_sha2_256_cipher_then_auth(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_zuc_eea3_cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_zuc_eia3_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_gmac_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_null_cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_snow3g_uea2_cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_kasumi_f8_cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k() #F
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_snow3g_uia2_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_kasumi_f9_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha1_hmac_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha1_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_ctr_cipher_then_auth(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_ctr_snow_3g_uia2_cipher_then_aut=
h(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_cmac_cipher_then_auth(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_3des_cbc_cipher_then_auth(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha1_hmac_cipher_then_auth(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_224_hmac_cipher_then_auth(self)=
:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_256_hmac_cipher_then_auth(self)=
:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_384_hmac_cipher_then_auth(self)=
:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_ctr_snow_3g_uia2_cipher_then_aut=
h(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_ctr_zuc_eia3_cipher_then_auth(se=
lf):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_ctr_aes_cmac_cipher_then_auth(se=
lf):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_zuc_eea3_snow3g_uia2_cipher_then_aut=
h(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_zuc_eea3_zuc_eia3_cipher_then_auth(s=
elf):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_zuc_eea3_aes_cmac_cipher_then_auth(s=
elf):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_snow3g_uea2_snow3g_uia2_cipher_then_=
auth(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_snow3g_uea2_zuc_eia3_cipher_then_aut=
h(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_snow3g_uea2_aes_cmac_cipher_then_aut=
h(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_md5_hmac_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_ctr_cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_3des_cbc_cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_224_hmac_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_256_hmac_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_384_hmac_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_512_hmac_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_aes_xts__cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_des_cbc_cipher_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_md5_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha512_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha384_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha256_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha224_auth_only(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_snow3g_uea2_snow3g_uia2(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha1_hmac_armv8(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_perf_mrvl_sha2_hmac_armv8(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_perf_cn10k()
> +
> + =C2=A0 =C2=A0def test_mrvl_ptest(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_func_cn10k()
> +
> + =C2=A0 =C2=A0def test_mrvl_burst(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_func_cn10k()
> +
> + =C2=A0 =C2=A0def test_mrvl_devtype(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_func_cn10k()
> +
> + =C2=A0 =C2=A0def test_mrvl_crypto_sha1_hmac_armv8(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_func_cn10k()
> +
> + =C2=A0 =C2=A0def test_mrvl_chacha20_poly1305_aead(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_func_cn10k()
> +
> + =C2=A0 =C2=A0def test_mrvl_crypto_sha2_hmac_armv8(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_func_cn10k()
> +
> + =C2=A0 =C2=A0def test_mrvl_buffer(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0self._crypto_func_cn10k()
> +
> =C2=A0 =C2=A0 =C2=A0# Private functions
> =C2=A0 =C2=A0 =C2=A0def _run_crypto_func(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0""" Runs Crypto functional=
 test.
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0Returns:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0None
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
> +
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if cc.is_test_skip(self):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return
> -
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0cores =3D ",".join(self.dut.get=
_core_list("1S/2C/1T"))
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0core_list =3D self.get_suite_cfg().get(&#=
39;core_list',"1S/2C/1T")
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0cores =3D ",".join(self.dut.get=
_core_list(core_list))
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0config =3D {"l": cores}
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0devices =3D self._get_crypto_device(=
1)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if not devices:
> @@ -206,12 +451,22 @@ class TestCryptoPerfCryptodevPerf(TestCase):
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0out =3D self.dut.send_command(
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"cat %s/%s.txt&qu=
ot; % (self.dut_file_dir, self.running_case), 30
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0)
> -
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0).strip()
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.verify("Error" not in=
 out, "Test function failed")
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.verify("failed" not i=
n out, "Test function failed")
> -
> - =C2=A0 =C2=A0def _run_crypto_perf(self):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0assert (out !=3D ""), "No =
output"
> +
> + =C2=A0 =C2=A0def _run_crypto_perf(self, **kwargs):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0""" Runs Crypto Performanc=
e test.
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0Args:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0**kwargs:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0expected: send_expec=
t match prompt
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0trim_whitespace: tri=
me whitespace from command output
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0Returns:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0None
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0expected =3D kwargs.get("expected&qu=
ot;, "#")
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0trim_whitespace =3D kwargs.get("trim=
_whitespace", True)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if cc.is_test_skip(self):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return "skip"=
;
>
> @@ -222,13 +477,14 @@ class TestCryptoPerfCryptodevPerf(TestCase):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return "skip"=
;
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0eal_opt_str =3D cc.get_eal_opt_str(s=
elf, devices)
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0crypto_perf_opt_str =3D self._get_crypto_=
perf_opt_str()
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0crypto_perf_opt_str =3D self._get_crypto_=
perf_opt_str(**kwargs)
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cmd_str =3D cc.get_dpdk_app_cmd_str(
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self._app_path, eal_op=
t_str, crypto_perf_opt_str
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0try:
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0out =3D self.dut.send_expec=
t(cmd_str, "#", 600)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0out =3D self.dut.send_expec=
t(cmd_str, expected, 600,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 trim_whi=
tespace=3Dtrim_whitespace)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0except Exception as ex:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.logger.error(ex)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0raise ex
> @@ -237,25 +493,44 @@ class TestCryptoPerfCryptodevPerf(TestCase):
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return results
>
> - =C2=A0 =C2=A0def _get_crypto_perf_opt_str(self, override_crypto_perf=
_opts=3D{}):
> + =C2=A0 =C2=A0def _get_crypto_perf_opt_str(self, **kwargs):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""get crypto perf app opt=
ion string
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0args:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0**kwargs:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0override_cryp=
to_perf_opts- Suite/Case specfic perf
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0app config to=
 overwrite defaults
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0Returns:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0crypto perf option string
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0"""
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0override_crypto_perf_opts =3D kwargs.get(=
"override_crypto_perf_opts", {})
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return cc.get_opt_str(
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self, self._default_cr=
ypto_perf_opts, override_crypto_perf_opts
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0)
>
> =C2=A0 =C2=A0 =C2=A0def _parse_output(self, output):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0try:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dtype =3D self.get_case_cfg=
().get('devtype')
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0match_str =3D r" =C2=
=A0 =C2=A0lcore id|#lcore id"
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0lines =3D output.split=
("\r\n")
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0line_nb =3D len(lines)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.logger.debug(&quo=
t;Total output lines: " + str(line_nb))
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for line_index in rang=
e(line_nb):
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if lines[line=
_index].startswith(" =C2=A0 =C2=A0lcore id"):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if re.match(m=
atch_str, lines[line_index]):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0self.logger.debug("data output line from: " + str(line_inde=
x))
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0break
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0data_line =3D line_index - =
1
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if dtype =3D=3D 'crypto=
_cn10k':
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0data_line =3D=
 line_index + 2
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0else:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0data_line =3D=
 line_index - 1
> +
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if len(lines[data_line].spl=
it(","))>1:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pattern =3D r=
e.compile(r',')
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0else:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pattern =3D r=
e.compile(r'\s+')
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0results =3D []
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pattern =3D re.compile(r&qu=
ot;\s+")
> +
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for line in lines[data=
_line:-1]:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0print(li=
ne)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0result =
=3D {}
> @@ -334,9 +609,15 @@ class TestCryptoPerfCryptodevPerf(TestCase):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_info[key] =3D valu=
e.strip()
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0core, thread =3D 0, 0
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0lcores =3D self.get_case_cfg()["=
;l"].split(",")
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if 'Core(s) per cluster' in out:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cl_soc1 =3D 'Core(s) pe=
r cluster'
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cl_soc2 =3D 'Cluster(s)=
'
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0else:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cl_soc1 =3D 'Core(s) pe=
r socket'
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cl_soc2 =3D 'Socket(s)&=
#39;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0for lcore in lcores[1:]:
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if int(lcore.strip()) < =
int(cpu_info["Core(s) per socket"]) * int(
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_info[&quo=
t;Socket(s)"]
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if int(lcore.strip()) < =
int(cpu_info[cl_soc1]) * int(
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_info[cl_s=
oc2]
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0core +=
=3D 1
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0thread +=
=3D 1
> @@ -362,6 +643,11 @@ class TestCryptoPerfCryptodevPerf(TestCase):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev =3D "crypto_s=
now3g"
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0elif self.get_case_cfg()["devty=
pe"] =3D=3D "crypto_zuc":
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev =3D "crypto_z=
uc"
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0elif self.get_case_cfg()["devtype&qu=
ot;] =3D=3D "crypto_cn10k":
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev =3D "crypto_cn10k&=
quot;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0vf =3D cc.get_qat_devices(s=
elf, cpm_num=3D1, num=3Dnum)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0device["a"] =3D &=
#39; -a '.join(vf)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0device["vdev"] =
=3D None
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0elif self.get_case_cfg()["devty=
pe"] =3D=3D "crypto_scheduler":
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev =3D "crypto_s=
cheduler"
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0w =3D cc.get_qat_devic=
es(self, cpm_num=3D3, num=3Dnum * 3)
> @@ -388,8 +674,8 @@ class TestCryptoPerfCryptodevPerf(TestCase):
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return device
>
> - =C2=A0 =C2=A0def _run_crypto_perf_throughput(self):
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0results =3D self._run_crypto_perf()
> + =C2=A0 =C2=A0def _run_crypto_perf_throughput(self, **kwargs):
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0results =3D self._run_crypto_perf(**kwarg=
s)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if results =3D=3D "skip":
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0self.verify(results, "test resu=
lts is none, Test Failed")
> diff --git a/tests/cryptodev_common.py b/tests/cryptodev_common.py
> index b550b468..91067b05 100644
> --- a/tests/cryptodev_common.py
> +++ b/tests/cryptodev_common.py
> @@ -8,7 +8,9 @@ from nics.net_device import GetNicObj
> =C2=A0conf =3D SuiteConf("cryptodev_sample")
>
>
> -def bind_qat_device(test_case, driver=3D"igb_uio"):
> +def bind_qat_device(test_case, driver=3D"igb_uio", generate=
_vfs=3DFalse,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0vf_count=3D2, drvr_type=3D'generic'):
> +
> =C2=A0 =C2=A0 =C2=A0if driver =3D=3D "vfio-pci":
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0test_case.dut.send_expect("modp=
robe vfio", "#", 10)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0test_case.dut.send_expect("modp=
robe vfio-pci", "#", 10)
> @@ -38,6 +40,8 @@ def bind_qat_device(test_case, driver=3D"igb_ui=
o"):
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0devfun_id =3D addr_array[2]
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pf_port =3D GetNicObj(test_case.dut,=
 domain_id, bus_id, devfun_id)
>
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0if generate_vfs:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pf_port.generate_sriov_vfs_=
linux(domain_id, bus_id, devfun_id, vf_count, drvr_type)
>
>
> Is this different from calling generate_sriov_vfs(), which I assume is=
 the "correct" behavior. There appears to be a common practice in=
 legacy DTS of templating out function names to call instead of using inher=
itance, so you will have a base function like bind_port(), and then that te=
mplates out calls to bind_port_linux(). bind_port_freebsd(), bind_port_wind=
ows() etc. It's a little strange but it is what it is and we should pro=
bably stick with the existing system if we are going to make additions. But=
, if there is a practical reason why you did it this way, then okay. :)
>
> I missed it initially, addressed it in updated patch.
>
>
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sriov_vfs_pci =3D pf_port.get_sriov_=
vfs_pci()
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if not sriov_vfs_pci:
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0raise Exception("=
can not get vf pci")
> @@ -51,6 +55,11 @@ def bind_qat_device(test_case, driver=3D"igb_u=
io"):
>
> =C2=A0 =C2=A0 =C2=A0test_case.dev =3D dev
>
> +def bind_mrvl_devices(test_case, driver=3D'vfio-pci', **kwarg=
s):
> + =C2=A0 =C2=A0pci_list =3D kwargs.get("pci_list").split()
> + =C2=A0 =C2=A0for pci in pci_list:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0test_case.dut.bind_eventdev_port(driver, =
pci)
> + =C2=A0 =C2=A0return pci_list
>
> =C2=A0def get_qat_devices(test_case, cpm_num=3DNone, num=3D1):
> =C2=A0 =C2=A0 =C2=A0if not cpm_num:
> --
> 2.25.1
>
--000000000000fc77a90627eabfa2--