From: "Hunt, David" <david.hunt@intel.com>
To: Radu Nicolau <radu.nicolau@intel.com>, dev@dpdk.org
Cc: chris.macnamara@intel.com, michael.j.glynn@intel.com
Subject: Re: [dpdk-dev] [PATCH v2 3/3] examples/l3fw-power: add high/regular performance cores option
Date: Tue, 26 Jun 2018 10:43:37 +0100 [thread overview]
Message-ID: <e068cc94-e6e6-62c9-5717-ff9777c95433@intel.com> (raw)
In-Reply-To: <1528711403-29776-3-git-send-email-radu.nicolau@intel.com>
On 11/6/2018 11:03 AM, Radu Nicolau wrote:
> Added high/regular performance core pinning configuration options
> that can be used in place of the existing 'config' option.
>
> '--high-perf-cores CORELIST' option allow the user to specify a
> high performance cores list; if this option is not used and the
> 'perf-config' option is used, the application will query the
> system using the rte_power library in order to get a list of
> available high performance cores. The cores that are considered
> high performance are the cores that have turbo enabled.
>
> '--perf-config (port,queue,hi_perf,lcore_index)'
> option is similar to the existing config option, the cores are specified
> as indices for bins containing high or regular performance cores.
>
> Example:
>
> l3fwd-power -l 6,7 -- -p 0xff \
> --high-perf-cores 6 --perf-config="(0,0,0,0),(1,0,1,0)"
>
> cores 6 and 7 are used, core 6 is specified as a high performance core.
> port 0 queue 0 will use a regular performance core, index 0 (core 7)
> port 1 queue 0 will use a high performance core, index 0 (core 6)
>
> Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
> ---
> examples/l3fwd-power/Makefile | 4 +-
> examples/l3fwd-power/main.c | 74 ++++++++++---
> examples/l3fwd-power/main.h | 20 ++++
> examples/l3fwd-power/meson.build | 4 +-
> examples/l3fwd-power/perf_core.c | 230 +++++++++++++++++++++++++++++++++++++++
> examples/l3fwd-power/perf_core.h | 12 ++
> 6 files changed, 323 insertions(+), 21 deletions(-)
> create mode 100644 examples/l3fwd-power/main.h
> create mode 100644 examples/l3fwd-power/perf_core.c
> create mode 100644 examples/l3fwd-power/perf_core.h
>
> diff --git a/examples/l3fwd-power/Makefile b/examples/l3fwd-power/Makefile
> index 390b7d6..1a46033 100644
> --- a/examples/l3fwd-power/Makefile
> +++ b/examples/l3fwd-power/Makefile
> @@ -1,11 +1,11 @@
> # SPDX-License-Identifier: BSD-3-Clause
> -# Copyright(c) 2010-2014 Intel Corporation
> +# Copyright(c) 2010-2018 Intel Corporation
>
> # binary name
> APP = l3fwd-power
>
> # all source are stored in SRCS-y
> -SRCS-y := main.c
> +SRCS-y := main.c perf_core.c
>
> # Build using pkg-config variables if possible
> $(shell pkg-config --exists libdpdk)
> diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c
> index 596d645..2268d54 100644
> --- a/examples/l3fwd-power/main.c
> +++ b/examples/l3fwd-power/main.c
> @@ -1,5 +1,5 @@
> /* SPDX-License-Identifier: BSD-3-Clause
> - * Copyright(c) 2010-2016 Intel Corporation
> + * Copyright(c) 2010-2018 Intel Corporation
> */
>
> #include <stdio.h>
> @@ -44,6 +44,9 @@
> #include <rte_power.h>
> #include <rte_spinlock.h>
>
> +#include "perf_core.h"
> +#include "main.h"
> +
> #define RTE_LOGTYPE_L3FWD_POWER RTE_LOGTYPE_USER1
>
> #define MAX_PKT_BURST 32
> @@ -155,14 +158,7 @@ struct lcore_rx_queue {
> #define MAX_RX_QUEUE_INTERRUPT_PER_PORT 16
>
>
> -#define MAX_LCORE_PARAMS 1024
> -struct lcore_params {
> - uint16_t port_id;
> - uint8_t queue_id;
> - uint8_t lcore_id;
> -} __rte_cache_aligned;
> -
> -static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
> +struct lcore_params lcore_params_array[MAX_LCORE_PARAMS];
> static struct lcore_params lcore_params_array_default[] = {
> {0, 0, 2},
> {0, 1, 2},
> @@ -175,8 +171,8 @@ static struct lcore_params lcore_params_array_default[] = {
> {3, 1, 3},
> };
>
> -static struct lcore_params * lcore_params = lcore_params_array_default;
> -static uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
> +struct lcore_params *lcore_params = lcore_params_array_default;
> +uint16_t nb_lcore_params = sizeof(lcore_params_array_default) /
> sizeof(lcore_params_array_default[0]);
>
> static struct rte_eth_conf port_conf = {
> @@ -1121,10 +1117,15 @@ print_usage(const char *prgname)
> {
> printf ("%s [EAL options] -- -p PORTMASK -P"
> " [--config (port,queue,lcore)[,(port,queue,lcore]]"
> + " [--high-perf-cores CORELIST"
> + " [--perf-config (port,queue,hi_perf,lcore_index)[,(port,queue,hi_perf,lcore_index]]"
> " [--enable-jumbo [--max-pkt-len PKTLEN]]\n"
> " -p PORTMASK: hexadecimal bitmask of ports to configure\n"
> " -P : enable promiscuous mode\n"
> " --config (port,queue,lcore): rx queues configuration\n"
> + " --high-perf-cores CORELIST: list of high performance cores\n"
> + " --perf-config: similar as config, cores specified as indices"
> + " for bins containing high or regular performance cores\n"
> " --no-numa: optional, disable numa awareness\n"
> " --enable-jumbo: enable jumbo frame"
> " which max packet len is PKTLEN in decimal (64-9600)\n"
> @@ -1234,6 +1235,8 @@ parse_args(int argc, char **argv)
> char *prgname = argv[0];
> static struct option lgopts[] = {
> {"config", 1, 0, 0},
> + {"perf-config", 1, 0, 0},
> + {"high-perf-cores", 1, 0, 0},
> {"no-numa", 0, 0, 0},
> {"enable-jumbo", 0, 0, 0},
> {CMD_LINE_OPT_PARSE_PTYPE, 0, 0, 0},
> @@ -1272,6 +1275,26 @@ parse_args(int argc, char **argv)
> }
>
> if (!strncmp(lgopts[option_index].name,
> + "perf-config", 11)) {
> + ret = parse_perf_config(optarg);
> + if (ret) {
> + printf("invalid perf-config\n");
> + print_usage(prgname);
> + return -1;
> + }
> + }
> +
> + if (!strncmp(lgopts[option_index].name,
> + "high-perf-cores", 15)) {
> + ret = parse_perf_core_list(optarg);
> + if (ret) {
> + printf("invalid high-perf-cores\n");
> + print_usage(prgname);
> + return -1;
> + }
> + }
> +
> + if (!strncmp(lgopts[option_index].name,
> "no-numa", 7)) {
> printf("numa is disabled \n");
> numa_on = 0;
> @@ -1609,6 +1632,23 @@ static int check_ptype(uint16_t portid)
>
> }
>
> +static int
> +init_power_library(void)
> +{
> + int ret = 0, lcore_id;
> + for (lcore_id = 0; lcore_id < RTE_MAX_LCORE; lcore_id++) {
> + if (rte_lcore_is_enabled(lcore_id)) {
> + /* init power management library */
> + ret = rte_power_init(lcore_id);
> + if (ret)
> + RTE_LOG(ERR, POWER,
> + "Library initialization failed on core %u\n",
> + lcore_id);
> + }
> + }
> + return ret;
> +}
> +
> int
> main(int argc, char **argv)
> {
> @@ -1643,6 +1683,12 @@ main(int argc, char **argv)
> if (ret < 0)
> rte_exit(EXIT_FAILURE, "Invalid L3FWD parameters\n");
>
> + if (init_power_library())
> + rte_exit(EXIT_FAILURE, "init_power_library failed\n");
> +
> + if (update_lcore_params() < 0)
> + rte_exit(EXIT_FAILURE, "update_lcore_params failed\n");
> +
> if (check_lcore_params() < 0)
> rte_exit(EXIT_FAILURE, "check_lcore_params failed\n");
>
> @@ -1773,12 +1819,6 @@ main(int argc, char **argv)
> if (rte_lcore_is_enabled(lcore_id) == 0)
> continue;
>
> - /* init power management library */
> - ret = rte_power_init(lcore_id);
> - if (ret)
> - RTE_LOG(ERR, POWER,
> - "Library initialization failed on core %u\n", lcore_id);
> -
> /* init timer structures for each enabled lcore */
> rte_timer_init(&power_timers[lcore_id]);
> hz = rte_get_timer_hz();
> diff --git a/examples/l3fwd-power/main.h b/examples/l3fwd-power/main.h
> new file mode 100644
> index 0000000..258de98
> --- /dev/null
> +++ b/examples/l3fwd-power/main.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2010-2018 Intel Corporation
> + */
> +
> +#ifndef _MAIN_H_
> +#define _MAIN_H_
> +
> +
> +#define MAX_LCORE_PARAMS 1024
> +struct lcore_params {
> + uint16_t port_id;
> + uint8_t queue_id;
> + uint8_t lcore_id;
> +} __rte_cache_aligned;
> +
> +extern struct lcore_params *lcore_params;
> +extern uint16_t nb_lcore_params;
> +extern struct lcore_params lcore_params_array[];
> +
> +#endif /* _MAIN_H_ */
> diff --git a/examples/l3fwd-power/meson.build b/examples/l3fwd-power/meson.build
> index f633a0f..20c8054 100644
> --- a/examples/l3fwd-power/meson.build
> +++ b/examples/l3fwd-power/meson.build
> @@ -1,5 +1,5 @@
> # SPDX-License-Identifier: BSD-3-Clause
> -# Copyright(c) 2017 Intel Corporation
> +# Copyright(c) 2018 Intel Corporation
>
> # meson file, for building this example as part of a main DPDK build.
> #
> @@ -11,5 +11,5 @@ if host_machine.system() != 'linux'
> endif
> deps += ['power', 'timer', 'lpm', 'hash']
> sources = files(
> - 'main.c'
> + 'main.c', 'perf_core.c'
> )
> diff --git a/examples/l3fwd-power/perf_core.c b/examples/l3fwd-power/perf_core.c
> new file mode 100644
> index 0000000..83948ea
> --- /dev/null
> +++ b/examples/l3fwd-power/perf_core.c
> @@ -0,0 +1,230 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2010-2018 Intel Corporation
> + */
> +
> +#include <stdio.h>
> +#include <string.h>
> +
> +#include <rte_common.h>
> +#include <rte_memory.h>
> +#include <rte_lcore.h>
> +#include <rte_power.h>
> +#include <rte_string_fns.h>
> +
> +#include "perf_core.h"
> +#include "main.h"
> +
> +
> +static uint16_t hp_lcores[RTE_MAX_LCORE];
> +static uint16_t nb_hp_lcores;
> +
> +struct perf_lcore_params {
> + uint16_t port_id;
> + uint8_t queue_id;
> + uint8_t high_perf;
> + uint8_t lcore_idx;
> +} __rte_cache_aligned;
> +
> +static struct perf_lcore_params prf_lc_prms[MAX_LCORE_PARAMS];
> +static uint16_t nb_prf_lc_prms;
> +
> +int
> +update_lcore_params(void)
> +{
> + uint8_t non_perf_lcores[RTE_MAX_LCORE];
> + uint16_t nb_non_perf_lcores = 0;
> + int i, j, ret;
> +
> + /* if perf-config option was not used do nothing */
> + if (nb_prf_lc_prms == 0)
> + return 0;
> +
> + /* if high-perf-cores option was not used query every available core */
> + if (nb_hp_lcores == 0) {
> + for (i = 0; i < RTE_MAX_LCORE; i++) {
> + if (rte_lcore_is_enabled(i)) {
> + struct rte_power_core_capabilities caps;
> + ret = rte_power_get_capabilities(i, &caps);
> + if (ret == 0 && caps.turbo) {
> + hp_lcores[nb_hp_lcores] = i;
> + nb_hp_lcores++;
> + }
> + }
> + }
> + }
> +
> + /* create a list on non high performance cores*/
> + for (i = 0; i < RTE_MAX_LCORE; i++) {
> + if (rte_lcore_is_enabled(i)) {
> + int hp = 0;
> + for (j = 0; j < nb_hp_lcores; j++) {
> + if (hp_lcores[j] == i) {
> + hp = 1;
> + break;
> + }
> + }
> + if (!hp)
> + non_perf_lcores[nb_non_perf_lcores++] = i;
> + }
> + }
> +
> + /* update the lcore config */
> + for (i = 0; i < nb_prf_lc_prms; i++) {
> + int lcore = -1;
> + if (prf_lc_prms[i].high_perf) {
> + if (prf_lc_prms[i].lcore_idx < nb_hp_lcores)
> + lcore = hp_lcores[prf_lc_prms[i].lcore_idx];
> + } else {
> + if (prf_lc_prms[i].lcore_idx < nb_non_perf_lcores)
> + lcore =
> + non_perf_lcores[prf_lc_prms[i].lcore_idx];
> + }
> +
> + if (lcore < 0) {
> + printf("Performance cores configuration error\n");
> + return -1;
> + }
> +
> + lcore_params_array[i].lcore_id = lcore;
> + lcore_params_array[i].queue_id = prf_lc_prms[i].queue_id;
> + lcore_params_array[i].port_id = prf_lc_prms[i].port_id;
> + }
> +
> + lcore_params = lcore_params_array;
> + nb_lcore_params = nb_prf_lc_prms;
> +
> + printf("Updated performance core configuration\n");
> + for (i = 0; i < nb_prf_lc_prms; i++)
> + printf("\t(%d,%d,%d)\n", lcore_params[i].port_id,
> + lcore_params[i].queue_id,
> + lcore_params[i].lcore_id);
> +
> + return 0;
> +}
> +
> +int
> +parse_perf_config(const char *q_arg)
> +{
> + char s[256];
> + const char *p, *p0 = q_arg;
> + char *end;
> + enum fieldnames {
> + FLD_PORT = 0,
> + FLD_QUEUE,
> + FLD_LCORE_HP,
> + FLD_LCORE_IDX,
> + _NUM_FLD
> + };
> + unsigned long int_fld[_NUM_FLD];
> + char *str_fld[_NUM_FLD];
> + int i;
> + unsigned int size;
> +
> + nb_prf_lc_prms = 0;
> +
> + while ((p = strchr(p0, '(')) != NULL) {
> + ++p;
> + p0 = strchr(p, ')');
> + if (p0 == NULL)
> + return -1;
> +
> + size = p0 - p;
> + if (size >= sizeof(s))
> + return -1;
> +
> + snprintf(s, sizeof(s), "%.*s", size, p);
> + if (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') !=
> + _NUM_FLD)
> + return -1;
> + for (i = 0; i < _NUM_FLD; i++) {
> + errno = 0;
> + int_fld[i] = strtoul(str_fld[i], &end, 0);
> + if (errno != 0 || end == str_fld[i] || int_fld[i] > 255)
> + return -1;
> + }
> + if (nb_prf_lc_prms >= MAX_LCORE_PARAMS) {
> + printf("exceeded max number of lcore params: %hu\n",
> + nb_prf_lc_prms);
> + return -1;
> + }
> + prf_lc_prms[nb_prf_lc_prms].port_id =
> + (uint8_t)int_fld[FLD_PORT];
> + prf_lc_prms[nb_prf_lc_prms].queue_id =
> + (uint8_t)int_fld[FLD_QUEUE];
> + prf_lc_prms[nb_prf_lc_prms].high_perf =
> + !!(uint8_t)int_fld[FLD_LCORE_HP];
> + prf_lc_prms[nb_prf_lc_prms].lcore_idx =
> + (uint8_t)int_fld[FLD_LCORE_IDX];
> + ++nb_prf_lc_prms;
> + }
> +
> + return 0;
> +}
> +
> +int
> +parse_perf_core_list(const char *corelist)
> +{
> + int i, idx = 0;
> + unsigned int count = 0;
> + char *end = NULL;
> + int min, max;
> +
> + if (corelist == NULL) {
> + printf("invalid core list\n");
> + return -1;
> + }
> +
> +
> + /* Remove all blank characters ahead and after */
> + while (isblank(*corelist))
> + corelist++;
> + i = strlen(corelist);
> + while ((i > 0) && isblank(corelist[i - 1]))
> + i--;
> +
> + /* Get list of cores */
> + min = RTE_MAX_LCORE;
> + do {
> + while (isblank(*corelist))
> + corelist++;
> + if (*corelist == '\0')
> + return -1;
> + errno = 0;
> + idx = strtoul(corelist, &end, 10);
> + if (errno || end == NULL)
> + return -1;
> + while (isblank(*end))
> + end++;
> + if (*end == '-') {
> + min = idx;
> + } else if ((*end == ',') || (*end == '\0')) {
> + max = idx;
> + if (min == RTE_MAX_LCORE)
> + min = idx;
> + for (idx = min; idx <= max; idx++) {
> + hp_lcores[count] = idx;
> + count++;
> + }
> + min = RTE_MAX_LCORE;
> + } else {
> + printf("invalid core list\n");
> + return -1;
> + }
> + corelist = end + 1;
> + } while (*end != '\0');
> +
> + if (count == 0) {
> + printf("invalid core list\n");
> + return -1;
> + }
> +
> + nb_hp_lcores = count;
> +
> + printf("Configured %d high performance cores\n", nb_hp_lcores);
> + for (i = 0; i < nb_hp_lcores; i++)
> + printf("\tHigh performance core %d %d\n",
> + i, hp_lcores[i]);
> +
> + return 0;
> +}
> +
> diff --git a/examples/l3fwd-power/perf_core.h b/examples/l3fwd-power/perf_core.h
> new file mode 100644
> index 0000000..7b7b747
> --- /dev/null
> +++ b/examples/l3fwd-power/perf_core.h
> @@ -0,0 +1,12 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2010-2018 Intel Corporation
> + */
> +
> +#ifndef _PERF_CORE_H_
> +#define _PERF_CORE_H_
> +
> +int parse_perf_config(const char *q_arg);
> +int parse_perf_core_list(const char *corelist);
> +int update_lcore_params(void);
> +
> +#endif /* _PERF_CORE_H_ */
Acked-by: David Hunt<david.hunt@intel.com>
next prev parent reply other threads:[~2018-06-26 9:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-06 10:47 [dpdk-dev] [PATCH 1/2] power: add get capabilities API Radu Nicolau
2018-06-06 10:47 ` [dpdk-dev] [PATCH 2/2] examples/l3fw-power: add high/regular performance cores option Radu Nicolau
2018-06-11 10:03 ` [dpdk-dev] [PATCH v2 1/3] power: add get capabilities API Radu Nicolau
2018-06-11 10:03 ` [dpdk-dev] [PATCH v2 2/3] test/power: add unit test for " Radu Nicolau
2018-06-26 9:43 ` Hunt, David
2018-06-11 10:03 ` [dpdk-dev] [PATCH v2 3/3] examples/l3fw-power: add high/regular performance cores option Radu Nicolau
2018-06-26 9:43 ` Hunt, David [this message]
2018-06-26 9:43 ` [dpdk-dev] [PATCH v2 1/3] power: add get capabilities API Hunt, David
2018-07-12 17:20 ` Thomas Monjalon
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