From: Ferruh Yigit <ferruh.yigit@amd.com>
To: Jesna K E <jesna.k.e@amd.com>, dev@dpdk.org
Cc: Selwin.Sebastian@amd.com
Subject: Re: [PATCH v1 3/3] net/axgbe: support TSO Implementation
Date: Wed, 15 Nov 2023 19:33:40 +0000 [thread overview]
Message-ID: <f58cbf1e-59eb-4dab-a66b-5636fcf83620@amd.com> (raw)
In-Reply-To: <20231111160006.455767-3-jesna.k.e@amd.com>
On 11/11/2023 4:00 PM, Jesna K E wrote:
> Signed-off-by: Jesna K E <jesna.k.e@amd.com>
>
Hi Jesna,
There are some reported build errors [1], can you please check them?
Also please provide some commit log, event it is brief.
[1]
https://mails.dpdk.org/archives/test-report/2023-November/508540.html
> ---
> drivers/net/axgbe/axgbe_common.h | 11 +
> drivers/net/axgbe/axgbe_dev.c | 19 ++
> drivers/net/axgbe/axgbe_ethdev.c | 1 +
> drivers/net/axgbe/axgbe_ethdev.h | 1 +
> drivers/net/axgbe/axgbe_rxtx.c | 305 +++++++++++++++----------
> drivers/net/axgbe/axgbe_rxtx_vec_sse.c | 1 +
> 6 files changed, 223 insertions(+), 115 deletions(-)
>
'doc/guides/nics/features/axgbe.ini' needs to be updated
> diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h
> index a5d11c5832..1face6f361 100644
> --- a/drivers/net/axgbe/axgbe_common.h
> +++ b/drivers/net/axgbe/axgbe_common.h
> @@ -162,6 +162,9 @@
> #define DMA_CH_SR 0x60
>
> /* DMA channel register entry bit positions and sizes */
> +//TSO
>
Please prefer /* */ comments
> +#define DMA_CH_CR_MSS_INDEX 0
> +#define DMA_CH_CR_MSS_WIDTH 14
> #define DMA_CH_CR_PBLX8_INDEX 16
> #define DMA_CH_CR_PBLX8_WIDTH 1
> #define DMA_CH_CR_SPH_INDEX 24
> @@ -1232,6 +1235,14 @@
> #define TX_CONTEXT_DESC3_VT_INDEX 0
> #define TX_CONTEXT_DESC3_VT_WIDTH 16
>
> +//TSO
> +#define TX_NORMAL_DESC3_TPL_INDEX 0
> +#define TX_NORMAL_DESC3_TPL_WIDTH 18
> +#define TX_NORMAL_DESC3_THL_INDEX 19
> +#define TX_NORMAL_DESC3_THL_WIDTH 4
> +#define TX_CONTEXT_DESC3_OSTC_INDEX 27
> +#define TX_CONTEXT_DESC3_OSTC_WIDTH 1
> +
> #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
> #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
> #define TX_NORMAL_DESC2_IC_INDEX 31
> diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c
> index 6a7fddffca..7e0d387fc3 100644
> --- a/drivers/net/axgbe/axgbe_dev.c
> +++ b/drivers/net/axgbe/axgbe_dev.c
> @@ -808,6 +808,24 @@ int axgbe_write_rss_lookup_table(struct axgbe_port *pdata)
> return 0;
> }
>
> +
>
here adds extra empty line
<...>
> @@ -843,7 +847,7 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,
>
> idx = AXGBE_GET_DESC_IDX(txq, txq->cur);
> desc = &txq->desc[idx];
> -
> + printf("tso::Inside axgbe_xmit_hw \n");
>
We are not allowed to use 'printf' for logging, but need to use logging
macros.
There are other instances of 'printf' usage in this patch.
<...>
> + } else {
> + /* Enable CRC and Pad Insertion */
> + AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CPC, 0);
> + /* Total msg length to transmit */
> + AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,
> + mbuf->pkt_len);
> + }
> +#if 0
>
Please remove unused code for upstreaming.
next prev parent reply other threads:[~2023-11-15 19:34 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-11 16:00 [PATCH v1 1/3] net/axgbe: packet size doesn't exceed the configured MTU Jesna K E
2023-11-11 16:00 ` [PATCH v1 2/3] net/axgbe: correct API call when offload enabled Jesna K E
2023-11-13 15:23 ` Ferruh Yigit
2023-11-13 16:55 ` Ferruh Yigit
2023-11-14 6:07 ` [PATCH v2] net/axgbe: invoke correct API when offloads enabled Jesna K E
2023-11-14 7:15 ` Jesna K E
2023-11-15 5:56 ` [PATCH v3] " Jesna K E
2023-11-15 11:57 ` Ferruh Yigit
2023-11-15 12:54 ` Sebastian, Selwin
2023-11-15 12:59 ` Ferruh Yigit
2023-11-11 16:00 ` [PATCH v1 3/3] net/axgbe: support TSO Implementation Jesna K E
2023-11-15 19:33 ` Ferruh Yigit [this message]
2023-11-16 9:44 ` [PATCH v2] net/axgbe: support TSO Jesna K E
2023-11-16 16:03 ` [PATCH v3] " Jesna K E
2023-11-17 18:34 ` Ferruh Yigit
2023-11-13 15:07 ` [PATCH v1 1/3] net/axgbe: packet size doesn't exceed the configured MTU Ferruh Yigit
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