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From: Maxime Coquelin <maxime.coquelin@redhat.com>
To: Hernan Vargas <hernan.vargas@intel.com>,
	dev@dpdk.org, gakhil@marvell.com, trix@redhat.com
Cc: nicolas.chautru@intel.com, qi.z.zhang@intel.com
Subject: Re: [PATCH v2 12/37] baseband/acc100: add LDPC transport block support
Date: Wed, 14 Sep 2022 22:47:46 +0200	[thread overview]
Message-ID: <f69305c6-9ae4-7f06-3883-250e51e58f9e@redhat.com> (raw)
In-Reply-To: <20220820023157.189047-13-hernan.vargas@intel.com>



On 8/20/22 04:31, Hernan Vargas wrote:
> Add LDPC enqueue functions to handle transport blocks.
> 
> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
>   drivers/baseband/acc100/rte_acc100_pmd.c | 197 ++++++++++++++++++++++-
>   1 file changed, 195 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c
> index e42748e8cc..81bae4d695 100644
> --- a/drivers/baseband/acc100/rte_acc100_pmd.c
> +++ b/drivers/baseband/acc100/rte_acc100_pmd.c
> @@ -2585,6 +2585,61 @@ enqueue_ldpc_enc_n_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op **ops,
>   	return num;
>   }
>   
> +/* Enqueue one encode operations for ACC100 device for a partial TB
> + * all codes blocks have same configuration multiplexed on the same descriptor
> + */
> +static inline void
> +enqueue_ldpc_enc_part_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op,
> +		uint16_t total_enqueued_descs, int16_t num_cbs, uint32_t e,
> +		uint16_t in_len_B, uint32_t out_len_B, uint32_t *in_offset,

Do not mix lower & upper cases in variable names.

> +		uint32_t *out_offset)
> +{
> +
> +	union acc100_dma_desc *desc = NULL;
> +	struct rte_mbuf *output_head, *output;
> +	int i, next_triplet;
> +	struct rte_bbdev_op_ldpc_enc *enc = &op->ldpc_enc;
> +
> +

Remove one new line.

> +	uint16_t desc_idx = ((q->sw_ring_head + total_enqueued_descs)
> +			& q->sw_ring_wrap_mask);
> +	desc = q->ring_addr + desc_idx;
> +	acc100_fcw_le_fill(op, &desc->req.fcw_le, num_cbs, e);
> +
> +	/** This could be done at polling */

Single * at the opening of the comment for consitency with the rest of
the code.

> +	acc100_header_init(&desc->req);
> +	desc->req.numCBs = num_cbs;
> +
> +	desc->req.m2dlen = 1 + num_cbs;
> +	desc->req.d2mlen = num_cbs;
> +	next_triplet = 1;
> +
> +	for (i = 0; i < num_cbs; i++) {
> +		desc->req.data_ptrs[next_triplet].address =
> +			rte_pktmbuf_iova_offset(enc->input.data,
> +					*in_offset);
> +		*in_offset += in_len_B;
> +		desc->req.data_ptrs[next_triplet].blen = in_len_B;
> +		next_triplet++;
> +		desc->req.data_ptrs[next_triplet].address =
> +				rte_pktmbuf_iova_offset(
> +						enc->output.data, *out_offset);
> +		*out_offset += out_len_B;
> +		desc->req.data_ptrs[next_triplet].blen = out_len_B;
> +		next_triplet++;
> +		enc->output.length += out_len_B;
> +		output_head = output = enc->output.data;
> +		mbuf_append(output_head, output, out_len_B);
> +	}
> +
> +#ifdef RTE_LIBRTE_BBDEV_DEBUG
> +	rte_memdump(stderr, "FCW", &desc->req.fcw_le,
> +			sizeof(desc->req.fcw_le) - 8);
> +	rte_memdump(stderr, "Req Desc.", desc, sizeof(*desc));
> +#endif
> +
> +}
> +
>   /* Enqueue one encode operations for ACC100 device in CB mode */
>   static inline int
>   enqueue_ldpc_enc_one_op_cb(struct acc100_queue *q, struct rte_bbdev_enc_op *op,
> @@ -2725,6 +2780,76 @@ enqueue_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op,
>   	return current_enqueued_cbs;
>   }
>   
> +/* Enqueue one encode operations for ACC100 device in TB mode.
> + * returns the number of descs used
> + */
> +static inline int
> +enqueue_ldpc_enc_one_op_tb(struct acc100_queue *q, struct rte_bbdev_enc_op *op,
> +		uint16_t enq_descs, uint8_t cbs_in_tb)
> +{
> +#ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE
> +	if (validate_ldpc_enc_op(op, q) == -1) {
> +		rte_bbdev_log(ERR, "LDPC encoder validation failed");
> +		return -EINVAL;
> +	}
> +#endif
> +	uint8_t num_a, num_b;
> +	uint16_t desc_idx;
> +	uint8_t r = op->ldpc_enc.tb_params.r;
> +	uint8_t cab =  op->ldpc_enc.tb_params.cab;
> +	union acc100_dma_desc *desc;
> +	uint16_t init_enq_descs = enq_descs;
> +	uint16_t input_len_B = ((op->ldpc_enc.basegraph == 1 ? 22 : 10) *
> +			op->ldpc_enc.z_c - op->ldpc_enc.n_filler) >> 3;
> +	if (check_bit(op->ldpc_enc.op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH))
> +		input_len_B -= 3;
> +
> +	if (r < cab) {
> +		num_a = cab - r;
> +		num_b = cbs_in_tb - cab;
> +	} else {
> +		num_a = 0;
> +		num_b = cbs_in_tb - r;
> +	}
> +	uint32_t in_offset = 0, out_offset = 0;
> +
> +	while (num_a > 0) {
> +		uint32_t e = op->ldpc_enc.tb_params.ea;
> +		uint32_t out_len_B = (e + 7) >> 3;
> +		uint8_t enq = RTE_MIN(num_a, ACC100_MUX_5GDL_DESC);
> +		num_a -= enq;
> +		enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B,
> +				out_len_B, &in_offset, &out_offset);
> +		enq_descs++;
> +	}
> +	while (num_b > 0) {
> +		uint32_t e = op->ldpc_enc.tb_params.eb;
> +		uint32_t out_len_B = (e + 7) >> 3;
> +		uint8_t enq = RTE_MIN(num_b, ACC100_MUX_5GDL_DESC);
> +		num_b -= enq;
> +		enqueue_ldpc_enc_part_tb(q, op, enq_descs, enq, e, input_len_B,
> +				out_len_B, &in_offset, &out_offset);
> +		enq_descs++;
> +	}
> +
> +	uint16_t return_descs = enq_descs - init_enq_descs;
> +	/* Keep total number of CBs in first TB */
> +	desc_idx = ((q->sw_ring_head + init_enq_descs)
> +			& q->sw_ring_wrap_mask);
> +	desc = q->ring_addr + desc_idx;
> +	desc->req.cbs_in_tb = return_descs; /** Actual number of descriptors */
> +	desc->req.op_addr = op;
> +
> +	/* Set SDone on last CB descriptor for TB mode. */
> +	desc_idx = ((q->sw_ring_head + enq_descs - 1)
> +			& q->sw_ring_wrap_mask);
> +	desc = q->ring_addr + desc_idx;
> +	desc->req.sdone_enable = 1;
> +	desc->req.irq_enable = q->irq_enable;
> +	desc->req.op_addr = op;
> +	return return_descs;
> +}
> +
>   #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE
>   /* Validates turbo decoder parameters */
>   static inline int
> @@ -3299,7 +3424,10 @@ enqueue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
>   	uint16_t current_enqueued_cbs = 0;
>   
>   #ifndef RTE_LIBRTE_BBDEV_SKIP_VALIDATE
> -	/* Validate op structure */
> +	if (cbs_in_tb == 0) {
> +		rte_bbdev_log(ERR, "Turbo decoder invalid number of CBs");
> +		return -EINVAL;
> +	}
>   	if (validate_dec_op(op, q) == -1) {
>   		rte_bbdev_log(ERR, "Turbo decoder validation rejected");
>   		return -EINVAL;
> @@ -3386,6 +3514,32 @@ enqueue_dec_one_op_tb(struct acc100_queue *q, struct rte_bbdev_dec_op *op,
>   	return current_enqueued_cbs;
>   }
>   
> +/* Calculates number of CBs in processed encoder TB based on 'r' and input
> + * length.
> + */
> +static inline uint8_t
> +get_num_cbs_in_tb_ldpc_enc(struct rte_bbdev_op_ldpc_enc *ldpc_enc)
> +{
> +	uint8_t c, r, crc24_bits = 0;
> +	uint16_t k = (ldpc_enc->basegraph == 1 ? 22 : 10) * ldpc_enc->z_c
> +		- ldpc_enc->n_filler;
> +	uint8_t cbs_in_tb = 0;
> +	int32_t length;
> +
> +	length = ldpc_enc->input.length;
> +	r = ldpc_enc->tb_params.r;
> +	c = ldpc_enc->tb_params.c;
> +	crc24_bits = 0;
> +	if (check_bit(ldpc_enc->op_flags, RTE_BBDEV_LDPC_CRC_24B_ATTACH))
> +		crc24_bits = 24;
> +	while (length > 0 && r < c) {
> +		length -= (k - crc24_bits) >> 3;
> +		r++;
> +		cbs_in_tb++;
> +	}
> +	return cbs_in_tb;
> +}
> +
>   /* Calculates number of CBs in processed encoder TB based on 'r' and input
>    * length.
>    */
> @@ -3667,6 +3821,45 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data,
>   	return i;
>   }
>   
> +/* Enqueue LDPC encode operations for ACC100 device in TB mode. */
> +static uint16_t
> +acc100_enqueue_ldpc_enc_tb(struct rte_bbdev_queue_data *q_data,
> +		struct rte_bbdev_enc_op **ops, uint16_t num)
> +{
> +	struct acc100_queue *q = q_data->queue_private;
> +	int32_t avail = acc100_ring_avail_enq(q);
> +	uint16_t i, enqueued_descs = 0;
> +	uint8_t cbs_in_tb;
> +	int descs_used;
> +
> +	for (i = 0; i < num; ++i) {
> +		cbs_in_tb = get_num_cbs_in_tb_ldpc_enc(&ops[i]->ldpc_enc);
> +		/* Check if there are available space for further processing */
> +		if (unlikely(avail - cbs_in_tb < 0)) {
> +			acc100_enqueue_ring_full(q_data);
> +			break;
> +		}
> +		descs_used = enqueue_ldpc_enc_one_op_tb(q, ops[i],
> +				enqueued_descs, cbs_in_tb);
> +		if (descs_used < 0) {
> +			acc100_enqueue_invalid(q_data);
> +			break;
> +		}
> +		enqueued_descs += descs_used;
> +		avail -= descs_used;
> +	}
> +	if (unlikely(enqueued_descs == 0))
> +		return 0; /* Nothing to enqueue */
> +
> +	acc100_dma_enqueue(q, enqueued_descs, &q_data->queue_stats);
> +
> +	/* Update stats */
> +	q_data->queue_stats.enqueued_count += i;
> +	q_data->queue_stats.enqueue_err_count += num - i;
> +
> +	return i;
> +}
> +
>   /* Check room in AQ for the enqueues batches into Qmgr */
>   static int32_t
>   acc100_aq_avail(struct rte_bbdev_queue_data *q_data, uint16_t num_ops)
> @@ -3704,7 +3897,7 @@ acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data,
>   	if (unlikely((aq_avail <= 0) || (num == 0)))
>   		return 0;
>   	if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK)
> -		return acc100_enqueue_enc_tb(q_data, ops, num);
> +		return acc100_enqueue_ldpc_enc_tb(q_data, ops, num);
>   	else
>   		return acc100_enqueue_ldpc_enc_cb(q_data, ops, num);
>   }


With minor comments taken into account:

Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>

Thanks,
Maxime


  reply	other threads:[~2022-09-14 20:47 UTC|newest]

Thread overview: 85+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-20  2:31 [PATCH v2 00/37] baseband/acc100: changes for 22.11 Hernan Vargas
2022-08-20  2:31 ` [PATCH v2 01/37] baseband/acc100: add enqueue status Hernan Vargas
2022-09-14 16:26   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 02/37] baseband/acc100: update ring availability calculation Hernan Vargas
2022-09-14 16:43   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 03/37] baseband/acc100: add function to check AQ availability Hernan Vargas
2022-09-14 17:00   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 04/37] baseband/acc100: free SW ring mem for reconfiguration Hernan Vargas
2022-09-14 19:22   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 05/37] baseband/acc100: memory leak fix Hernan Vargas
2022-09-14  8:50   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 06/37] baseband/acc100: add default e value for FCW Hernan Vargas
2022-09-14 19:24   ` Maxime Coquelin
2022-09-15 11:00   ` Thomas Monjalon
2022-09-16  1:12     ` Chautru, Nicolas
2022-09-16  7:11       ` Thomas Monjalon
2022-08-20  2:31 ` [PATCH v2 07/37] baseband/acc100: add LDPC encoder padding function Hernan Vargas
2022-09-14 19:35   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 08/37] baseband/acc100: add scatter-gather support Hernan Vargas
2022-09-14 20:09   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 09/37] baseband/acc100: add HARQ index helper function Hernan Vargas
2022-09-14 20:16   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 10/37] baseband/acc100: avoid mux for small inbound frames Hernan Vargas
2022-09-14 20:18   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 11/37] baseband/acc100: separate validation functions from debug Hernan Vargas
2022-09-14 20:35   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 12/37] baseband/acc100: add LDPC transport block support Hernan Vargas
2022-09-14 20:47   ` Maxime Coquelin [this message]
2022-08-20  2:31 ` [PATCH v2 13/37] baseband/acc10x: limit cases for HARQ pruning Hernan Vargas
2022-09-15  7:37   ` Maxime Coquelin
2022-09-16  0:31     ` Chautru, Nicolas
2022-08-20  2:31 ` [PATCH v2 14/37] baseband/acc100: update validate LDPC enc/dec Hernan Vargas
2022-09-15  7:43   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 15/37] baseband/acc100: add workaround for deRM corner cases Hernan Vargas
2022-09-15  8:15   ` Maxime Coquelin
2022-09-16  1:20     ` Chautru, Nicolas
2022-08-20  2:31 ` [PATCH v2 16/37] baseband/acc100: add ring companion address Hernan Vargas
2022-09-15  9:09   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 17/37] baseband/acc100: configure PMON control registers Hernan Vargas
2022-09-15  9:12   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 18/37] baseband/acc100: implement configurable queue depth Hernan Vargas
2022-09-15  9:52   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 19/37] baseband/acc100: add queue stop operation Hernan Vargas
2022-09-15  9:55   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 20/37] baseband/acc100: check turbo dec/enc input Hernan Vargas
2022-09-15 10:01   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 21/37] baseband/acc100: check for unlikely operation vals Hernan Vargas
2022-09-15 10:02   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 22/37] baseband/acc100: enforce additional check on FCW Hernan Vargas
2022-09-15 10:12   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 23/37] baseband/acc100: update uplink CB input length Hernan Vargas
2022-09-15 10:12   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 24/37] baseband/acc100: rename ldpc encode function arg Hernan Vargas
2022-09-15 10:14   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 25/37] baseband/acc100: update log messages Hernan Vargas
2022-09-15 10:14   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 26/37] baseband/acc100: allocate ring/queue mem when NULL Hernan Vargas
2022-09-15 10:15   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 27/37] baseband/acc100: store FCW from first CB descriptor Hernan Vargas
2022-09-15 10:18   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 28/37] baseband/acc100: make desc optimization optional Hernan Vargas
2022-09-15 10:19   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 29/37] baseband/acc100: update device info Hernan Vargas
2022-09-15 10:20   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 30/37] baseband/acc100: reduce input length for CRC24B Hernan Vargas
2022-09-15 10:21   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 31/37] baseband/acc100: fix clearing PF IR outside handler Hernan Vargas
2022-09-15 10:22   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 32/37] baseband/acc100: fix debug print for LDPC FCW Hernan Vargas
2022-09-15 10:23   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 33/37] baseband/acc100: set device min alignment to 1 Hernan Vargas
2022-09-15 10:24   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 34/37] baseband/acc100: update meson file sdk dependency Hernan Vargas
2022-09-15 10:31   ` Maxime Coquelin
2022-09-15 10:57     ` Thomas Monjalon
2022-09-16  0:39       ` Chautru, Nicolas
2022-08-20  2:31 ` [PATCH v2 35/37] baseband/acc100: add protection for NULL HARQ input Hernan Vargas
2022-09-15 11:33   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 36/37] baseband/acc100: make HARQ layout memory 4GB Hernan Vargas
2022-09-15 11:33   ` Maxime Coquelin
2022-08-20  2:31 ` [PATCH v2 37/37] baseband/acc100: reset pointer after rte_free Hernan Vargas
2022-09-15 11:34   ` Maxime Coquelin
2022-08-23 15:59 ` [EXT] [PATCH v2 00/37] baseband/acc100: changes for 22.11 Akhil Goyal
2022-08-24 18:23   ` Chautru, Nicolas
2022-09-06 20:03 ` Chautru, Nicolas

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