From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3FE44A04F5 for ; Thu, 12 Dec 2019 03:43:05 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 037E923D; Thu, 12 Dec 2019 03:43:05 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 8146723D for ; Thu, 12 Dec 2019 03:43:02 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Dec 2019 18:43:01 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,304,1571727600"; d="scan'208";a="245532418" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga002.fm.intel.com with ESMTP; 11 Dec 2019 18:43:00 -0800 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 18:43:00 -0800 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 11 Dec 2019 18:42:59 -0800 Received: from shsmsx101.ccr.corp.intel.com ([169.254.1.19]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.236]) with mapi id 14.03.0439.000; Thu, 12 Dec 2019 10:42:58 +0800 From: "Sun, GuinanX" To: Kevin Traynor CC: "Ye, Xiaolong" , dpdk stable Thread-Topic: patch 'net/ixgbe: fix MACsec setting' has been queued to LTS release 18.11.6 Thread-Index: AQHVsGnU4RQhIhZkdkKBqUr6wkDudae1yb3Q Date: Thu, 12 Dec 2019 02:42:57 +0000 Message-ID: <05758BDAD7FC8E4BAED63D0390A8A9557EE22E@SHSMSX101.ccr.corp.intel.com> References: <20191211212702.27851-1-ktraynor@redhat.com> <20191211212702.27851-4-ktraynor@redhat.com> In-Reply-To: <20191211212702.27851-4-ktraynor@redhat.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-stable] patch 'net/ixgbe: fix MACsec setting' has been queued to LTS release 18.11.6 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, Kevin macsec fix has two patches: http://patches.dpdk.org/patch/62265/ and http://patches.dpdk.org/patch/63196/ The 62265 patch is used to fix the problem that the macsec setting is inval= id when the port is stopped. The 63196 patch is used to fix the QoS sample application performance drop = issue caused by 62265. Please must merge patch 63196 after merging patch 62265. Best Regards Guinan Sun > -----Original Message----- > From: Kevin Traynor [mailto:ktraynor@redhat.com] > Sent: Thursday, December 12, 2019 5:26 AM > To: Sun, GuinanX > Cc: Ye, Xiaolong ; dpdk stable > Subject: patch 'net/ixgbe: fix MACsec setting' has been queued to LTS rel= ease > 18.11.6 >=20 > Hi, >=20 > FYI, your patch has been queued to LTS release 18.11.6 >=20 > Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. > It will be pushed if I get no objections before 12/17/19. So please shout= if > anyone has objections. >=20 > Also note that after the patch there's a diff of the upstream commit vs t= he patch > applied to the branch. This will indicate if there was any rebasing neede= d to > apply to the stable branch. If there were code changes for rebasing > (ie: not only metadata diffs), please double check that the rebase was co= rrectly > done. >=20 > Queued patches are on a temporary branch at: > https://github.com/kevintraynor/dpdk-stable-queue >=20 > This queued commit can be viewed at: > https://github.com/kevintraynor/dpdk-stable- > queue/commit/7137dc35798febc3ab6738921eab092ca5c4ac0e >=20 > Thanks. >=20 > Kevin. >=20 > --- > From 7137dc35798febc3ab6738921eab092ca5c4ac0e Mon Sep 17 00:00:00 > 2001 > From: Guinan Sun > Date: Thu, 31 Oct 2019 11:31:52 +0000 > Subject: [PATCH] net/ixgbe: fix MACsec setting >=20 > [ upstream commit 50556c88104cbc0096e90f454dc137258be2099f ] >=20 > MACsec setting is not valid when port is stopped. > In order to make it valid, the patch changes the setting to where port is= started. >=20 > Fixes: 597f9fafe13b ("app/testpmd: convert to new Tx offloads API") >=20 > Signed-off-by: Guinan Sun > Reviewed-by: Xiaolong Ye > --- > drivers/net/ixgbe/ixgbe_ethdev.c | 149 ++++++++++++++++++++++++++++++ > drivers/net/ixgbe/ixgbe_ethdev.h | 19 ++++ > drivers/net/ixgbe/rte_pmd_ixgbe.c | 125 ++----------------------- > 3 files changed, 175 insertions(+), 118 deletions(-) >=20 > diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_e= thdev.c > index 74de2ff4e..1336236ba 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.c > +++ b/drivers/net/ixgbe/ixgbe_ethdev.c > @@ -2591,4 +2591,6 @@ ixgbe_dev_start(struct rte_eth_dev *dev) > struct ixgbe_tm_conf *tm_conf =3D > IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); > + struct ixgbe_macsec_setting *macsec_ctrl =3D > + IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data- > >dev_private); >=20 > PMD_INIT_FUNC_TRACE(); > @@ -2831,4 +2833,7 @@ skip_link_setup: > ixgbe_dev_link_update(dev, 0); >=20 > + /* setup the macsec ctrl register */ > + ixgbe_dev_macsec_register_enable(dev, macsec_ctrl); > + > return 0; >=20 > @@ -2859,4 +2864,7 @@ ixgbe_dev_stop(struct rte_eth_dev *dev) > PMD_INIT_FUNC_TRACE(); >=20 > + /* disable mecsec register */ > + ixgbe_dev_macsec_register_disable(dev); > + > rte_eal_alarm_cancel(ixgbe_dev_setup_link_alarm_handler, dev); >=20 > @@ -8679,4 +8687,145 @@ ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev > *dev) } >=20 > +void > +ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, > + struct ixgbe_macsec_setting *macsec_setting) > { > + struct ixgbe_macsec_setting *macsec =3D > + IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data- > >dev_private); > + > + macsec->encrypt_en =3D macsec_setting->encrypt_en; > + macsec->replayprotect_en =3D macsec_setting->replayprotect_en; } > + > +void > +ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev) { > + struct ixgbe_macsec_setting *macsec =3D > + IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data- > >dev_private); > + > + macsec->encrypt_en =3D 0; > + macsec->replayprotect_en =3D 0; > +} > + > +void > +ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, > + struct ixgbe_macsec_setting *macsec_setting) > { > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + uint32_t ctrl; > + uint8_t en =3D macsec_setting->encrypt_en; > + uint8_t rp =3D macsec_setting->replayprotect_en; > + > + /** > + * Workaround: > + * As no ixgbe_disable_sec_rx_path equivalent is > + * implemented for tx in the base code, and we are > + * not allowed to modify the base code in DPDK, so > + * just call the hand-written one directly for now. > + * The hardware support has been checked by > + * ixgbe_disable_sec_rx_path(). > + */ > + ixgbe_disable_sec_tx_path_generic(hw); > + > + /* Enable Ethernet CRC (required by MACsec offload) */ > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_HLREG0); > + ctrl |=3D IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; > + IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); > + > + /* Enable the TX and RX crypto engines */ > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); > + ctrl &=3D ~IXGBE_SECTXCTRL_SECTX_DIS; > + IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); > + > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); > + ctrl &=3D ~IXGBE_SECRXCTRL_SECRX_DIS; > + IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); > + > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); > + ctrl &=3D ~IXGBE_SECTX_MINSECIFG_MASK; > + ctrl |=3D 0x3; > + IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); > + > + /* Enable SA lookup */ > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); > + ctrl &=3D ~IXGBE_LSECTXCTRL_EN_MASK; > + ctrl |=3D en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : > + IXGBE_LSECTXCTRL_AUTH; > + ctrl |=3D IXGBE_LSECTXCTRL_AISCI; > + ctrl &=3D ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; > + ctrl |=3D IXGBE_MACSEC_PNTHRSH & > IXGBE_LSECTXCTRL_PNTHRSH_MASK; > + IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); > + > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); > + ctrl &=3D ~IXGBE_LSECRXCTRL_EN_MASK; > + ctrl |=3D IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; > + ctrl &=3D ~IXGBE_LSECRXCTRL_PLSH; > + if (rp) > + ctrl |=3D IXGBE_LSECRXCTRL_RP; > + else > + ctrl &=3D ~IXGBE_LSECRXCTRL_RP; > + IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); > + > + /* Start the data paths */ > + ixgbe_enable_sec_rx_path(hw); > + /** > + * Workaround: > + * As no ixgbe_enable_sec_rx_path equivalent is > + * implemented for tx in the base code, and we are > + * not allowed to modify the base code in DPDK, so > + * just call the hand-written one directly for now. > + */ > + ixgbe_enable_sec_tx_path_generic(hw); > +} > + > +void > +ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev) { > + struct ixgbe_hw *hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data- > >dev_private); > + uint32_t ctrl; > + > + /** > + * Workaround: > + * As no ixgbe_disable_sec_rx_path equivalent is > + * implemented for tx in the base code, and we are > + * not allowed to modify the base code in DPDK, so > + * just call the hand-written one directly for now. > + * The hardware support has been checked by > + * ixgbe_disable_sec_rx_path(). > + */ > + ixgbe_disable_sec_tx_path_generic(hw); > + > + /* Disable the TX and RX crypto engines */ > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); > + ctrl |=3D IXGBE_SECTXCTRL_SECTX_DIS; > + IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); > + > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); > + ctrl |=3D IXGBE_SECRXCTRL_SECRX_DIS; > + IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); > + > + /* Disable SA lookup */ > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); > + ctrl &=3D ~IXGBE_LSECTXCTRL_EN_MASK; > + ctrl |=3D IXGBE_LSECTXCTRL_DISABLE; > + IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); > + > + ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); > + ctrl &=3D ~IXGBE_LSECRXCTRL_EN_MASK; > + ctrl |=3D IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; > + IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); > + > + /* Start the data paths */ > + ixgbe_enable_sec_rx_path(hw); > + /** > + * Workaround: > + * As no ixgbe_enable_sec_rx_path equivalent is > + * implemented for tx in the base code, and we are > + * not allowed to modify the base code in DPDK, so > + * just call the hand-written one directly for now. > + */ > + ixgbe_enable_sec_tx_path_generic(hw); > +} > + > RTE_PMD_REGISTER_PCI(net_ixgbe, rte_ixgbe_pmd); > RTE_PMD_REGISTER_PCI_TABLE(net_ixgbe, pci_id_ixgbe_map); diff --git > a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h > index 5023fa13f..418adfa3d 100644 > --- a/drivers/net/ixgbe/ixgbe_ethdev.h > +++ b/drivers/net/ixgbe/ixgbe_ethdev.h > @@ -361,4 +361,9 @@ struct rte_flow { > }; >=20 > +struct ixgbe_macsec_setting { > + uint8_t encrypt_en; > + uint8_t replayprotect_en; > +}; > + > /* > * Statistics counters collected by the MACsec @@ -467,4 +472,5 @@ struc= t > ixgbe_adapter { > struct ixgbe_hw_stats stats; > struct ixgbe_macsec_stats macsec_stats; > + struct ixgbe_macsec_setting macsec_setting; > struct ixgbe_hw_fdir_info fdir; > struct ixgbe_interrupt intr; > @@ -519,4 +525,7 @@ int ixgbe_vf_representor_uninit(struct rte_eth_dev > *ethdev); > (&((struct ixgbe_adapter *)adapter)->macsec_stats) >=20 > +#define IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(adapter) \ > + (&((struct ixgbe_adapter *)adapter)->macsec_setting) > + > #define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \ > (&((struct ixgbe_adapter *)adapter)->intr) @@ -737,4 +746,14 @@ int > ixgbe_config_rss_filter(struct rte_eth_dev *dev, > struct ixgbe_rte_flow_rss_conf *conf, bool add); >=20 > +void ixgbe_dev_macsec_register_enable(struct rte_eth_dev *dev, > + struct ixgbe_macsec_setting *macsec_setting); > + > +void ixgbe_dev_macsec_register_disable(struct rte_eth_dev *dev); > + > +void ixgbe_dev_macsec_setting_save(struct rte_eth_dev *dev, > + struct ixgbe_macsec_setting *macsec_setting); > + > +void ixgbe_dev_macsec_setting_reset(struct rte_eth_dev *dev); > + > static inline int > ixgbe_ethertype_filter_lookup(struct ixgbe_filter_info *filter_info, dif= f --git > a/drivers/net/ixgbe/rte_pmd_ixgbe.c b/drivers/net/ixgbe/rte_pmd_ixgbe.c > index 3a874f9a9..49d538ef1 100644 > --- a/drivers/net/ixgbe/rte_pmd_ixgbe.c > +++ b/drivers/net/ixgbe/rte_pmd_ixgbe.c > @@ -515,7 +515,6 @@ int > rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp) { > - struct ixgbe_hw *hw; > struct rte_eth_dev *dev; > - uint32_t ctrl; > + struct ixgbe_macsec_setting macsec_setting; >=20 > RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); @@ -523,72 > +522,10 @@ rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t > rp) > dev =3D &rte_eth_devices[port]; >=20 > - if (!is_ixgbe_supported(dev)) > - return -ENOTSUP; > + macsec_setting.encrypt_en =3D en; > + macsec_setting.replayprotect_en =3D rp; >=20 > - hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > + ixgbe_dev_macsec_setting_save(dev, &macsec_setting); >=20 > - /* Stop the data paths */ > - if (ixgbe_disable_sec_rx_path(hw) !=3D IXGBE_SUCCESS) > - return -ENOTSUP; > - /** > - * Workaround: > - * As no ixgbe_disable_sec_rx_path equivalent is > - * implemented for tx in the base code, and we are > - * not allowed to modify the base code in DPDK, so > - * just call the hand-written one directly for now. > - * The hardware support has been checked by > - * ixgbe_disable_sec_rx_path(). > - */ > - ixgbe_disable_sec_tx_path_generic(hw); > - > - /* Enable Ethernet CRC (required by MACsec offload) */ > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_HLREG0); > - ctrl |=3D IXGBE_HLREG0_TXCRCEN | IXGBE_HLREG0_RXCRCSTRP; > - IXGBE_WRITE_REG(hw, IXGBE_HLREG0, ctrl); > - > - /* Enable the TX and RX crypto engines */ > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); > - ctrl &=3D ~IXGBE_SECTXCTRL_SECTX_DIS; > - IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); > - > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); > - ctrl &=3D ~IXGBE_SECRXCTRL_SECRX_DIS; > - IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); > - > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); > - ctrl &=3D ~IXGBE_SECTX_MINSECIFG_MASK; > - ctrl |=3D 0x3; > - IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, ctrl); > - > - /* Enable SA lookup */ > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); > - ctrl &=3D ~IXGBE_LSECTXCTRL_EN_MASK; > - ctrl |=3D en ? IXGBE_LSECTXCTRL_AUTH_ENCRYPT : > - IXGBE_LSECTXCTRL_AUTH; > - ctrl |=3D IXGBE_LSECTXCTRL_AISCI; > - ctrl &=3D ~IXGBE_LSECTXCTRL_PNTHRSH_MASK; > - ctrl |=3D IXGBE_MACSEC_PNTHRSH & > IXGBE_LSECTXCTRL_PNTHRSH_MASK; > - IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); > - > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); > - ctrl &=3D ~IXGBE_LSECRXCTRL_EN_MASK; > - ctrl |=3D IXGBE_LSECRXCTRL_STRICT << IXGBE_LSECRXCTRL_EN_SHIFT; > - ctrl &=3D ~IXGBE_LSECRXCTRL_PLSH; > - if (rp) > - ctrl |=3D IXGBE_LSECRXCTRL_RP; > - else > - ctrl &=3D ~IXGBE_LSECRXCTRL_RP; > - IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); > - > - /* Start the data paths */ > - ixgbe_enable_sec_rx_path(hw); > - /** > - * Workaround: > - * As no ixgbe_enable_sec_rx_path equivalent is > - * implemented for tx in the base code, and we are > - * not allowed to modify the base code in DPDK, so > - * just call the hand-written one directly for now. > - */ > - ixgbe_enable_sec_tx_path_generic(hw); > + ixgbe_dev_macsec_register_enable(dev, &macsec_setting); >=20 > return 0; > @@ -598,7 +535,5 @@ int > rte_pmd_ixgbe_macsec_disable(uint16_t port) { > - struct ixgbe_hw *hw; > struct rte_eth_dev *dev; > - uint32_t ctrl; >=20 > RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); @@ -606,53 > +541,7 @@ rte_pmd_ixgbe_macsec_disable(uint16_t port) > dev =3D &rte_eth_devices[port]; >=20 > - if (!is_ixgbe_supported(dev)) > - return -ENOTSUP; > + ixgbe_dev_macsec_setting_reset(dev); >=20 > - hw =3D IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); > - > - /* Stop the data paths */ > - if (ixgbe_disable_sec_rx_path(hw) !=3D IXGBE_SUCCESS) > - return -ENOTSUP; > - /** > - * Workaround: > - * As no ixgbe_disable_sec_rx_path equivalent is > - * implemented for tx in the base code, and we are > - * not allowed to modify the base code in DPDK, so > - * just call the hand-written one directly for now. > - * The hardware support has been checked by > - * ixgbe_disable_sec_rx_path(). > - */ > - ixgbe_disable_sec_tx_path_generic(hw); > - > - /* Disable the TX and RX crypto engines */ > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECTXCTRL); > - ctrl |=3D IXGBE_SECTXCTRL_SECTX_DIS; > - IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, ctrl); > - > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); > - ctrl |=3D IXGBE_SECRXCTRL_SECRX_DIS; > - IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, ctrl); > - > - /* Disable SA lookup */ > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECTXCTRL); > - ctrl &=3D ~IXGBE_LSECTXCTRL_EN_MASK; > - ctrl |=3D IXGBE_LSECTXCTRL_DISABLE; > - IXGBE_WRITE_REG(hw, IXGBE_LSECTXCTRL, ctrl); > - > - ctrl =3D IXGBE_READ_REG(hw, IXGBE_LSECRXCTRL); > - ctrl &=3D ~IXGBE_LSECRXCTRL_EN_MASK; > - ctrl |=3D IXGBE_LSECRXCTRL_DISABLE << IXGBE_LSECRXCTRL_EN_SHIFT; > - IXGBE_WRITE_REG(hw, IXGBE_LSECRXCTRL, ctrl); > - > - /* Start the data paths */ > - ixgbe_enable_sec_rx_path(hw); > - /** > - * Workaround: > - * As no ixgbe_enable_sec_rx_path equivalent is > - * implemented for tx in the base code, and we are > - * not allowed to modify the base code in DPDK, so > - * just call the hand-written one directly for now. > - */ > - ixgbe_enable_sec_tx_path_generic(hw); > + ixgbe_dev_macsec_register_disable(dev); >=20 > return 0; > -- > 2.21.0 >=20 > --- > Diff of the applied patch vs upstream commit (please double-check if no= n- > empty: > --- > --- - 2019-12-11 21:24:13.077637869 +0000 > +++ 0004-net-ixgbe-fix-MACsec-setting.patch 2019-12-11 > 21:24:12.552653594 +0000 > @@ -1 +1 @@ > -From 50556c88104cbc0096e90f454dc137258be2099f Mon Sep 17 00:00:00 > 2001 > +From 7137dc35798febc3ab6738921eab092ca5c4ac0e Mon Sep 17 00:00:00 > 2001 > @@ -5,0 +6,2 @@ > +[ upstream commit 50556c88104cbc0096e90f454dc137258be2099f ] > + > @@ -11 +12,0 @@ > -Cc: stable@dpdk.org > @@ -22 +23 @@ > -index 3c7624f3a..06414d110 100644 > +index 74de2ff4e..1336236ba 100644 > @@ -25 +26 @@ > -@@ -2543,4 +2543,6 @@ ixgbe_dev_start(struct rte_eth_dev *dev) > +@@ -2591,4 +2591,6 @@ ixgbe_dev_start(struct rte_eth_dev *dev) > @@ -32 +33 @@ > -@@ -2795,4 +2797,7 @@ skip_link_setup: > +@@ -2831,4 +2833,7 @@ skip_link_setup: > @@ -40 +41 @@ > -@@ -2826,4 +2831,7 @@ ixgbe_dev_stop(struct rte_eth_dev *dev) > +@@ -2859,4 +2864,7 @@ ixgbe_dev_stop(struct rte_eth_dev *dev) > @@ -48 +49 @@ > -@@ -8817,4 +8825,145 @@ ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev > *dev) > +@@ -8679,4 +8687,145 @@ ixgbe_clear_all_l2_tn_filter(struct rte_eth_dev > +*dev) > @@ -195 +196 @@ > -index 6e9ed2e10..5da6923a1 100644 > +index 5023fa13f..418adfa3d 100644 > @@ -198 +199 @@ > -@@ -366,4 +366,9 @@ struct rte_flow { > +@@ -361,4 +361,9 @@ struct rte_flow { > @@ -208 +209 @@ > -@@ -472,4 +477,5 @@ struct ixgbe_adapter { > +@@ -467,4 +472,5 @@ struct ixgbe_adapter { > @@ -214 +215 @@ > -@@ -524,4 +530,7 @@ int ixgbe_vf_representor_uninit(struct rte_eth_dev > *ethdev); > +@@ -519,4 +525,7 @@ int ixgbe_vf_representor_uninit(struct rte_eth_dev > +*ethdev); > @@ -222 +223 @@ > -@@ -742,4 +751,14 @@ int ixgbe_config_rss_filter(struct rte_eth_dev *dev= , > +@@ -737,4 +746,14 @@ int ixgbe_config_rss_filter(struct rte_eth_dev > +*dev, > @@ -238 +239 @@ > -index 9514f2cf5..073fe1e23 100644 > +index 3a874f9a9..49d538ef1 100644 > @@ -241 +242 @@ > -@@ -516,7 +516,6 @@ int > +@@ -515,7 +515,6 @@ int > @@ -250 +251 @@ > -@@ -524,72 +523,10 @@ rte_pmd_ixgbe_macsec_enable(uint16_t port, > uint8_t en, uint8_t rp) > +@@ -523,72 +522,10 @@ rte_pmd_ixgbe_macsec_enable(uint16_t port, > +uint8_t en, uint8_t rp) > @@ -327 +328 @@ > -@@ -599,7 +536,5 @@ int > +@@ -598,7 +535,5 @@ int > @@ -335 +336 @@ > -@@ -607,53 +542,7 @@ rte_pmd_ixgbe_macsec_disable(uint16_t port) > +@@ -606,53 +541,7 @@ rte_pmd_ixgbe_macsec_disable(uint16_t port)