From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BF541A0C4B for ; Thu, 8 Jul 2021 14:09:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A86F2415EC; Thu, 8 Jul 2021 14:09:18 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id A68004014F; Thu, 8 Jul 2021 14:09:15 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10038"; a="196769486" X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="196769486" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jul 2021 05:09:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,222,1620716400"; d="scan'208";a="498402310" Received: from irsmsx603.ger.corp.intel.com ([163.33.146.9]) by fmsmga002.fm.intel.com with ESMTP; 08 Jul 2021 05:09:12 -0700 Received: from shsmsx601.ccr.corp.intel.com (10.109.6.141) by irsmsx603.ger.corp.intel.com (163.33.146.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2242.4; Thu, 8 Jul 2021 13:09:10 +0100 Received: from shsmsx601.ccr.corp.intel.com ([10.109.6.141]) by SHSMSX601.ccr.corp.intel.com ([10.109.6.141]) with mapi id 15.01.2242.010; Thu, 8 Jul 2021 20:09:08 +0800 From: "Zhang, Qi Z" To: Joyce Kong , "Xing, Beilei" , "ruifeng.wang@arm.com" , "honnappa.nagarahalli@arm.com" , "Richardson, Bruce" , "Zhang, Helin" CC: "dev@dpdk.org" , "stable@dpdk.org" , "nd@arm.com" Thread-Topic: [PATCH v3 2/2] net/i40e: replace SMP barrier with thread fence Thread-Index: AQHXcjPgn79d19TRw0ycP+68GlyG/qs4/M8Q Date: Thu, 8 Jul 2021 12:09:08 +0000 Message-ID: <061d231c5ff848a19be50a62aed44087@intel.com> References: <20210604073405.14880-1-joyce.kong@arm.com> <20210706065404.25137-1-joyce.kong@arm.com> <20210706065404.25137-3-joyce.kong@arm.com> In-Reply-To: <20210706065404.25137-3-joyce.kong@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-reaction: no-action dlp-version: 11.5.1.3 dlp-product: dlpe-windows x-originating-ip: [10.239.127.36] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-stable] [PATCH v3 2/2] net/i40e: replace SMP barrier with thread fence X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" > -----Original Message----- > From: Joyce Kong > Sent: Tuesday, July 6, 2021 2:54 PM > To: Xing, Beilei ; Zhang, Qi Z ; > ruifeng.wang@arm.com; honnappa.nagarahalli@arm.com; Richardson, Bruce > ; Zhang, Helin > Cc: dev@dpdk.org; stable@dpdk.org; nd@arm.com > Subject: [PATCH v3 2/2] net/i40e: replace SMP barrier with thread fence >=20 > Simply replace the SMP barrier with atomic thread fence for i40e hw ring = sacn, > if there is no synchronization point. >=20 > Signed-off-by: Joyce Kong > Reviewed-by: Ruifeng Wang > --- > drivers/net/i40e/i40e_rxtx.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c = index > 9aaabfd92..86e2f083e 100644 > --- a/drivers/net/i40e/i40e_rxtx.c > +++ b/drivers/net/i40e/i40e_rxtx.c > @@ -482,7 +482,8 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) > I40E_RXD_QW1_STATUS_SHIFT; > } >=20 > - rte_smp_rmb(); > + /* This barrier is to order loads of different words in the descriptor= */ > + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); Now for x86, you actually replace a compiler barrier with a memory fence, t= his may have potential performance impact which need additional resource to= investigate=20 So there are 2 options: 1. if you want this patch be merged into DPDK 21.08, please change this for= ARM only. 2. you can wait for our update for x86 but I guess it will miss 21.08. What do you think? Btw for patch 1/2, I think I can merge it independently right? >=20 > /* Compute how many status bits were set */ > for (j =3D 0, nb_dd =3D 0; j < I40E_LOOK_AHEAD; j++) { > -- > 2.17.1