From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1224E47177 for ; Sun, 4 Jan 2026 03:54:00 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A4F4B40273; Sun, 4 Jan 2026 03:53:59 +0100 (CET) Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) by mails.dpdk.org (Postfix) with ESMTP id C3E5340273 for ; Sun, 4 Jan 2026 03:53:57 +0100 (CET) X-QQ-mid: esmtpsz18t1767495232t0d1162b8 X-QQ-Originating-IP: 5d0Hmu5QMoOvN0w/A8hkDjndGeISE9NPfx4GRINEZL4= Received: from w-MS-7E16.trustnetic.com ( [122.231.228.237]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 04 Jan 2026 10:53:47 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 3907511000695800100 EX-QQ-RecipientCnt: 2 From: Jiawen Wu To: stable@dpdk.org Cc: Jiawen Wu Subject: [PATCH 23.11] net/txgbe: fix FDIR input mask Date: Sun, 4 Jan 2026 10:53:45 +0800 Message-ID: <0E33CDCEF4A04199+20260104025345.79694-1-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.48.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: esmtpsz:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz6b-0 X-QQ-XMAILINFO: M+0YV038q5N1uf43XXmIu4POx3Fp9wKbUA3Aip4n9klBAi8xhbptU2Eo Tru17o/Gt9tlEsGTH6J0xyYgMFqDSuF9X2SpitVxV0gukd+SNRrLCdlKdab/x/NblhRCS7o fFoC0ANIXd8Q+SuBSCOBWv7SR9K/J2GjGJSls/94SEhoeMizwF8cBRAtDU1Ith+Asuahcxp MJL2M6cc+Xb3SmMJR1EppdLTsR2+Q4tuUHj/3AXLBbP+a0njDrNeOjdC5aVUAvkMVroV/gT rx+TexuUhiz3o5UJ9/Gxh2TU105a0vHEf06jt4utfqjA6Lxd2v0UXxrhNH5WZE75YSbIhZa TRPbPDrhxaENvD8ViLxzAO/UhHAY+SztRjUFPnydPk6FpFQTzpjB6jiparImXnl5hXgljXr 5F/CSZs0LUmo9k3AGKFr7YUH/VVw49trZaSaZjZ0LEb4fE9y64Pqo/Z0hATehzUmBrZADYH GNra5TxJ0wEPLFlu5VswjOPseBIdKUbHx9imY16/SOS7HJXGC3o2H1e67nA51nOGZGhGND+ zTQ4BQzYttNTfZXhiTTHeIz6uPmEG2uMN9iBpr6MIRw8s00zEMjgBSlCbJXDbNzCkCbNXBA Iwx2SkwaIXOwXnFdKw9ILfJh0JQ97dDoEOs/U8AzySwYT+/aDmwIldXgC1ep6R/Z0QgwBxl 9GA1G+91IwQ4ijlCpn3NlUwiUBdYbEtFWE+TSO49ri6I+aLRmpvNCSQqlF7Zas+OdwFTuwT bz6ZvATOwGfvASqxuELIsSr6FbgUIFNoVhX2W1LqzrwXOv4EcgJ85TtPDSeqX1N9a77DObq HhYXNELVzx208zBHXr4FXAZkpDeW6qfEPrKyg4uK/6Kbd2Bp8ifUJeeldBaqivimMZEb3Oe BZmPScAdmDX5SetrHZHsDwKhBZsh/zdm47xvUl+anS3kjE6BxfEn3Mj3tQ2xgAsW8NrW9H1 YCPlE0HildE1OYwYxHYK5oUt4hbn5mmi6oERpqnSKadq5SU6h+dDjeAse/g0yvgpd81ddhA tYdefhXkuU63fnjI5M X-QQ-XMRINFO: NS+P29fieYNwqS3WCnRCOn9D1NpZuCnCRA== X-QQ-RECHKSPAM: 0 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit a2d4de27109033d5061da44aed919bf46cfd7ca9 ] Fix FDIR mask settings to comply with the hardware configuration. And mask out the spec field instead of manually setting it to 0. There are some requirements of mask in hardware: 1) IPv4 mask should be little-endian. 2) Ipv6 source address mask has only 16 bits, one bit of mask corresponds to one byte of spec. 3) IPv6 dest address is only supported to perfect match the low 8 bits, so it is not taken into account for support in the driver. Fixes: ea230dda16ad ("net/txgbe: configure flow director filter") Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_fdir.c | 49 +++++++++++++++++++++++++++++----- drivers/net/txgbe/txgbe_flow.c | 8 ++---- 2 files changed, 45 insertions(+), 12 deletions(-) diff --git a/drivers/net/txgbe/txgbe_fdir.c b/drivers/net/txgbe/txgbe_fdir.c index 8d181db33f..6b83a7379d 100644 --- a/drivers/net/txgbe/txgbe_fdir.c +++ b/drivers/net/txgbe/txgbe_fdir.c @@ -165,6 +165,15 @@ configure_fdir_flags(const struct rte_eth_fdir_conf *conf, return 0; } +static inline uint16_t +txgbe_reverse_fdir_bitmasks(uint16_t mask) +{ + mask = ((mask & 0x5555) << 1) | ((mask & 0xAAAA) >> 1); + mask = ((mask & 0x3333) << 2) | ((mask & 0xCCCC) >> 2); + mask = ((mask & 0x0F0F) << 4) | ((mask & 0xF0F0) >> 4); + return ((mask & 0x00FF) << 8) | ((mask & 0xFF00) >> 8); +} + int txgbe_fdir_set_input_mask(struct rte_eth_dev *dev) { @@ -206,15 +215,15 @@ txgbe_fdir_set_input_mask(struct rte_eth_dev *dev) wr32(hw, TXGBE_FDIRUDPMSK, ~fdirtcpm); wr32(hw, TXGBE_FDIRSCTPMSK, ~fdirtcpm); - /* Store source and destination IPv4 masks (big-endian) */ - wr32(hw, TXGBE_FDIRSIP4MSK, ~info->mask.src_ipv4_mask); - wr32(hw, TXGBE_FDIRDIP4MSK, ~info->mask.dst_ipv4_mask); + /* Store source and destination IPv4 masks (little-endian) */ + wr32(hw, TXGBE_FDIRSIP4MSK, rte_be_to_cpu_32(~info->mask.src_ipv4_mask)); + wr32(hw, TXGBE_FDIRDIP4MSK, rte_be_to_cpu_32(~info->mask.dst_ipv4_mask)); /* * Store source and destination IPv6 masks (bit reversed) */ - fdiripv6m = TXGBE_FDIRIP6MSK_DST(info->mask.dst_ipv6_mask) | - TXGBE_FDIRIP6MSK_SRC(info->mask.src_ipv6_mask); + fdiripv6m = txgbe_reverse_fdir_bitmasks(info->mask.dst_ipv6_mask) << 16; + fdiripv6m |= txgbe_reverse_fdir_bitmasks(info->mask.src_ipv6_mask); wr32(hw, TXGBE_FDIRIP6MSK, ~fdiripv6m); return 0; @@ -636,8 +645,14 @@ fdir_write_perfect_filter(struct txgbe_hw *hw, fdircmd |= TXGBE_FDIRPICMD_QP(queue); fdircmd |= TXGBE_FDIRPICMD_POOL(input->vm_pool); - if (input->flow_type & TXGBE_ATR_L3TYPE_IPV6) + if (input->flow_type & TXGBE_ATR_L3TYPE_IPV6) { + /* use SIP4 to store LS Dword of the Source iPv6 address */ + wr32(hw, TXGBE_FDIRPISIP4, be_to_le32(input->src_ip[3])); + wr32(hw, TXGBE_FDIRPISIP6(0), be_to_le32(input->src_ip[2])); + wr32(hw, TXGBE_FDIRPISIP6(1), be_to_le32(input->src_ip[1])); + wr32(hw, TXGBE_FDIRPISIP6(2), be_to_le32(input->src_ip[0])); fdircmd |= TXGBE_FDIRPICMD_IP6; + } wr32(hw, TXGBE_FDIRPICMD, fdircmd); PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash); @@ -783,6 +798,26 @@ txgbe_remove_fdir_filter(struct txgbe_hw_fdir_info *fdir_info, return 0; } +static void +txgbe_fdir_mask_input(struct txgbe_hw_fdir_mask *mask, + struct txgbe_atr_input *input) +{ + int i; + + if (input->flow_type & TXGBE_ATR_L3TYPE_IPV6) { + for (i = 0; i < 16; i++) { + if (!(mask->src_ipv6_mask & (1 << i))) + input->src_ip[i / 4] &= ~(0xFF << ((i % 4) * 8)); + } + } else { + input->src_ip[0] &= mask->src_ipv4_mask; + input->dst_ip[0] &= mask->dst_ipv4_mask; + } + + input->src_port &= mask->src_port_mask; + input->dst_port &= mask->dst_port_mask; +} + int txgbe_fdir_filter_program(struct rte_eth_dev *dev, struct txgbe_fdir_rule *rule, @@ -805,6 +840,8 @@ txgbe_fdir_filter_program(struct rte_eth_dev *dev, if (fdir_mode >= RTE_FDIR_MODE_PERFECT) is_perfect = TRUE; + txgbe_fdir_mask_input(&info->mask, &rule->input); + if (is_perfect) { fdirhash = atr_compute_perfect_hash(&rule->input, TXGBE_DEV_FDIR_CONF(dev)->pballoc); diff --git a/drivers/net/txgbe/txgbe_flow.c b/drivers/net/txgbe/txgbe_flow.c index 8ac29a0351..006e0b9759 100644 --- a/drivers/net/txgbe/txgbe_flow.c +++ b/drivers/net/txgbe/txgbe_flow.c @@ -1834,9 +1834,7 @@ txgbe_parse_fdir_filter_normal(struct rte_eth_dev *dev __rte_unused, /* check dst addr mask */ for (j = 0; j < 16; j++) { - if (ipv6_mask->hdr.dst_addr[j] == UINT8_MAX) { - rule->mask.dst_ipv6_mask |= 1 << j; - } else if (ipv6_mask->hdr.dst_addr[j] != 0) { + if (ipv6_mask->hdr.dst_addr[j] != 0) { memset(rule, 0, sizeof(struct txgbe_fdir_rule)); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, @@ -2597,9 +2595,7 @@ txgbe_parse_fdir_filter_tunnel(const struct rte_flow_attr *attr, /* check dst addr mask */ for (j = 0; j < 16; j++) { - if (ipv6_mask->hdr.dst_addr[j] == UINT8_MAX) { - rule->mask.dst_ipv6_mask |= 1 << j; - } else if (ipv6_mask->hdr.dst_addr[j] != 0) { + if (ipv6_mask->hdr.dst_addr[j] != 0) { memset(rule, 0, sizeof(struct txgbe_fdir_rule)); rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, -- 2.48.1