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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-Network-Message-Id: 23bfd20e-233c-4f3b-cd40-08d6654adc62 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Dec 2018 00:42:32.8639 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB4311 Subject: [dpdk-stable] [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2018 00:42:35 -0000 From: Shahed Shaikh [ backported from upstream commit 797ce8eec7c1b9e37dd9398403e9bc888cca0013 = ] Management firmware does not properly clean IGU block in PF FLR flow which may result in undelivered attentions for link events from default status block. Add a workaround in PMD to execute extra IGU cleanup right after PF FLR is done. Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before load req= uest") Signed-off-by: Shahed Shaikh --- drivers/net/qede/base/ecore_dev.c | 7 +++++++ drivers/net/qede/base/ecore_int.c | 32 ++++++++++++++++++++++++++++++++ drivers/net/qede/base/ecore_int.h | 1 + drivers/net/qede/base/mcp_public.h | 2 ++ drivers/net/qede/base/reg_addr.h | 15 +++++++++++++++ 5 files changed, 57 insertions(+) diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecor= e_dev.c index 092606b..6a3046d 100644 --- a/drivers/net/qede/base/ecore_dev.c +++ b/drivers/net/qede/base/ecore_dev.c @@ -4096,6 +4096,13 @@ void ecore_prepare_hibernate(struct ecore_dev *p_dev= ) rc =3D ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); if (rc !=3D ECORE_SUCCESS) DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n"); + + /* Workaround for MFW issue where PF FLR does not cleanup + * IGU block + */ + if (!(p_hwfn->mcp_info->capabilities & + FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP)) + ecore_pf_flr_igu_cleanup(p_hwfn); } =20 /* Check if mdump logs/data are present and update the epoch value */ diff --git a/drivers/net/qede/base/ecore_int.c b/drivers/net/qede/base/ecor= e_int.c index 61e36a4..b2582aa 100644 --- a/drivers/net/qede/base/ecore_int.c +++ b/drivers/net/qede/base/ecore_int.c @@ -2679,3 +2679,35 @@ enum _ecore_status_t ecore_int_get_sb_dbg(struct eco= re_hwfn *p_hwfn, =20 return ECORE_SUCCESS; } + +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn) +{ + struct ecore_ptt *p_ptt =3D p_hwfn->p_main_ptt; + struct ecore_ptt *p_dpc_ptt =3D ecore_get_reserved_ptt(p_hwfn, + RESERVED_PTT_DPC); + int i; + + /* Do not reorder the following cleanup sequence */ + /* Ack all attentions */ + ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff); + + /* Clear driver attention */ + ecore_wr(p_hwfn, p_dpc_ptt, + ((p_hwfn->rel_pf_id << 3) + MISC_REG_AEU_GENERAL_ATTN_0), 0); + + /* Clear per-PF IGU registers to restore them as if the IGU + * was reset for this PF + */ + ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); + ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); + ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); + + /* Execute IGU clean up*/ + ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1); + + /* Clear Stats */ + ecore_wr(p_hwfn, p_ptt, IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, 0); + + for (i =3D 0; i < IGU_REG_PBA_STS_PF_SIZE; i++) + ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0); +} diff --git a/drivers/net/qede/base/ecore_int.h b/drivers/net/qede/base/ecor= e_int.h index 563051c..ebee68b 100644 --- a/drivers/net/qede/base/ecore_int.h +++ b/drivers/net/qede/base/ecore_int.h @@ -258,4 +258,5 @@ enum _ecore_status_t ecore_int_set_timer_res(struct eco= re_hwfn *p_hwfn, enum _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn *p_hw= fn, struct ecore_ptt *p_ptt); =20 +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn); #endif /* __ECORE_INT_H__ */ diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp= _public.h index 81ca663..b83b241 100644 --- a/drivers/net/qede/base/mcp_public.h +++ b/drivers/net/qede/base/mcp_public.h @@ -1777,6 +1777,8 @@ struct public_drv_mb { #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 /* MFW supports EEE */ #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 +/* MFW support complete IGU cleanup upon FLR */ +#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP 0x00000080 /* MFW supports virtual link */ #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 =20 diff --git a/drivers/net/qede/base/reg_addr.h b/drivers/net/qede/base/reg_a= ddr.h index ad15d28..8f226ad 100644 --- a/drivers/net/qede/base/reg_addr.h +++ b/drivers/net/qede/base/reg_addr.h @@ -332,6 +332,21 @@ 0x180820UL #define IGU_REG_ATTN_MSG_ADDR_H \ 0x180824UL +#define IGU_REG_LEADING_EDGE_LATCH \ + 0x18082cUL +#define IGU_REG_TRAILING_EDGE_LATCH \ + 0x180830UL +#define IGU_REG_ATTENTION_ACK_BITS \ + 0x180838UL +#define IGU_REG_PBA_STS_PF \ + 0x180d20UL +#define IGU_REG_PF_FUNCTIONAL_CLEANUP \ + 0x181210UL +#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \ + 0x18042cUL +#define IGU_REG_PBA_STS_PF_SIZE 5 +#define IGU_REG_PBA_STS_PF \ + 0x180d20UL #define MISC_REG_AEU_GENERAL_ATTN_0 \ 0x008400UL #define CAU_REG_SB_ADDR_MEMORY \ --=20 1.7.10.3