From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 36A151B3B4 for ; Thu, 31 Jan 2019 03:35:26 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jan 2019 18:35:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,543,1539673200"; d="scan'208";a="315058051" Received: from dipei-st-npg.sh.intel.com ([10.67.110.220]) by fmsmga006.fm.intel.com with ESMTP; 30 Jan 2019 18:35:24 -0800 From: Andy Pei To: qabuild@intel.com Cc: andy.pei@intel.com, rosen.xu@intel.com, stable@dpdk.org Date: Thu, 31 Jan 2019 10:31:34 +0800 Message-Id: <1548901896-65591-5-git-send-email-andy.pei@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1548901896-65591-1-git-send-email-andy.pei@intel.com> References: <1548901896-65591-1-git-send-email-andy.pei@intel.com> Subject: [dpdk-stable] [DPDK 5/7] bus/ifpga: add a shared data structure to struct rte_afu_device X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2019 02:35:26 -0000 Add a data structure rte_afu_shared to data structure rte_afu_device. Struct rte_afu_shared contains a rte_spinlock_t and a void pointer. This struct rte_afu_shared will be used in net/vbng. Fixes: 05fa3d4a6539 ("bus/ifpga: add Intel FPGA bus library") Cc: rosen.xu@intel.com Cc: stable@dpdk.org Signed-off-by: Andy Pei --- drivers/bus/ifpga/rte_bus_ifpga.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/bus/ifpga/rte_bus_ifpga.h b/drivers/bus/ifpga/rte_bus_ifpga.h index 0bf43ba..820eeaa 100644 --- a/drivers/bus/ifpga/rte_bus_ifpga.h +++ b/drivers/bus/ifpga/rte_bus_ifpga.h @@ -17,6 +17,7 @@ #include #include +#include /** Name of Intel FPGA Bus */ #define IFPGA_BUS_NAME ifpga @@ -60,6 +61,11 @@ struct rte_afu_pr_conf { #define AFU_PRI_STR_SIZE (PCI_PRI_STR_SIZE + 8) +struct rte_afu_shared { + rte_spinlock_t lock; + void *data; +}; + /** * A structure describing a AFU device. */ @@ -71,6 +77,7 @@ struct rte_afu_device { uint32_t num_region; /**< number of regions found */ struct rte_mem_resource mem_resource[PCI_MAX_RESOURCE]; /**< AFU Memory Resource */ + struct rte_afu_shared shared; struct rte_intr_handle intr_handle; /**< Interrupt handle */ struct rte_afu_driver *driver; /**< Associated driver */ char path[IFPGA_BUS_BITSTREAM_PATH_MAX_LEN]; -- 1.8.3.1