From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 2EE84A00E6 for ; Thu, 18 Apr 2019 07:26:40 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C2FF91B907; Thu, 18 Apr 2019 07:26:39 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id B30101B907; Thu, 18 Apr 2019 07:26:38 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Apr 2019 22:26:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,364,1549958400"; d="scan'208";a="292519389" Received: from dpdk6.bj.intel.com ([172.16.182.192]) by orsmga004.jf.intel.com with ESMTP; 17 Apr 2019 22:26:36 -0700 From: Wei Zhao To: dev@dpdk.org Cc: stable@dpdk.org, qi.z.zhang@intel.com, Wei Zhao Date: Thu, 18 Apr 2019 12:58:15 +0800 Message-Id: <1555563495-47769-1-git-send-email-wei.zhao1@intel.com> X-Mailer: git-send-email 2.7.5 Subject: [dpdk-stable] [PATCH] net/iavf: fix queue interrupt for ICE X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Enable CLEARPBA bit is required by ice NIC of A0/A1 version to enable Tx and Rx queue interrupt. Also enable CLEARPBA bit does no impact on IAVF behaviour when be hosted by other devices, so we can make it as default. Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt") Cc: stable@dpdk.org Signed-off-by: Wei Zhao --- drivers/net/iavf/iavf_ethdev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index 846e604..57819dd 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -1015,11 +1015,13 @@ iavf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) PMD_DRV_LOG(INFO, "MISC is also enabled for control"); IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01, IAVFINT_DYN_CTL01_INTENA_MASK | + IAVFINT_DYN_CTL01_CLEARPBA_MASK | IAVFINT_DYN_CTL01_ITR_INDX_MASK); } else { IAVF_WRITE_REG(hw, IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START), IAVFINT_DYN_CTLN1_INTENA_MASK | + IAVFINT_DYN_CTL01_CLEARPBA_MASK | IAVFINT_DYN_CTLN1_ITR_INDX_MASK); } -- 2.7.5