From: Matan Azrad <matan@nvidia.com>
To: Maxime Coquelin <maxime.coquelin@redhat.com>
Cc: dev@dpdk.org, stable@dpdk.org
Subject: [dpdk-stable] [PATCH] vdpa/mlx5: fix completion queue assertion
Date: Wed, 2 Sep 2020 08:34:59 +0000 [thread overview]
Message-ID: <1599035699-358487-1-git-send-email-matan@nvidia.com> (raw)
The CQ configuration enables the collapse feature in HW what cause HW to
write all the completions in the first CQE.
When this feature is enabled the HW doesn't switch the owner bit when it
starts a new cycle of the CQ, not like working without the collapse
feature.
The current SW CQ polling wrongly added an assertion to validate the
owner bit switch what causes a panic in debug mode.
Remove the aforementioned assertion.
Fixes: c5f714e50b0e ("vdpa/mlx5: optimize completion queue poll")
Cc: stable@dpdk.org
Signed-off-by: Matan Azrad <matan@nvidia.com>
Acked-by: Xueming Li <xuemingl@nvidia.com>
---
drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
index 5a2d4fb..742ee62 100644
--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c
+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c
@@ -205,8 +205,6 @@
comp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;
if (comp) {
cq->cq_ci += comp;
- MLX5_ASSERT(!!(cq->cq_ci & cq_size) ==
- MLX5_CQE_OWNER(last_word.op_own));
MLX5_ASSERT(MLX5_CQE_OPCODE(last_word.op_own) !=
MLX5_CQE_INVALID);
if (unlikely(!(MLX5_CQE_OPCODE(last_word.op_own) ==
--
1.8.3.1
next reply other threads:[~2020-09-02 8:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-02 8:34 Matan Azrad [this message]
2020-09-18 10:33 ` Maxime Coquelin
2020-09-18 12:29 ` Maxime Coquelin
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