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From: Michael Baum <michaelba@nvidia.com>
To: dev@dpdk.org
Cc: Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,
Viacheslav Ovsiienko <viacheslavo@nvidia.com>, stable@dpdk.org
Date: Wed, 18 Nov 2020 17:00:09 +0000
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References: <1605718811-18652-1-git-send-email-michaelba@nvidia.com>
Subject: [dpdk-stable] [PATCH 5/7] regex/mlx5: improve error messages in RXP
rules flush
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During the rules flush, the rxp_poll_csr_for_value function is called
twice. The rxp_poll_csr_for_value function can fail for two reasons:
1. It could not read the value from register, in which case the
function returns -1.
2. It read a value, but not the value it expected to receive. In this
case it returns -EBUZY.
When the function fails it prints an error message that is relevant only
for a second type of failure. Moreover, for failure of the first type it
prints a value of an uninitialized variable.
In case of success, the function prints a debug message about the number
of cycles it took. This line was probably copied by mistake, since the
variable it reads from, is always equal to 0 and is not an indicator of
the number of cycles.
Remove the incorrect line about the cycles, and reduce the error print
only for the relevant error.
Fixes: b34d816363b5 ("regex/mlx5: support rules import")
Cc: stable@dpdk.org
Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
---
drivers/regex/mlx5/mlx5_rxp.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c
index ba78cc0..fcbc766 100644
--- a/drivers/regex/mlx5/mlx5_rxp.c
+++ b/drivers/regex/mlx5/mlx5_rxp.c
@@ -179,12 +179,14 @@
count, ~0,
MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);
if (ret < 0) {
- DRV_LOG(ERR, "Rules not rx by RXP: credit: %d, depth: %d", val,
- fifo_depth);
+ if (ret == -EBUSY)
+ DRV_LOG(ERR, "Rules not rx by RXP: credit: %d, depth:"
+ " %d", val, fifo_depth);
+ else
+ DRV_LOG(ERR, "CSR poll failed, can't read value!");
return ret;
}
DRV_LOG(DEBUG, "RTRU FIFO depth: 0x%x", fifo_depth);
- DRV_LOG(DEBUG, "Rules flush took %d cycles.", ret);
ret = mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
&val);
if (ret) {
@@ -203,10 +205,12 @@
MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE,
MLX5_RXP_POLL_CSR_FOR_VALUE_TIMEOUT, id);
if (ret < 0) {
- DRV_LOG(ERR, "Rules update timeout: 0x%08X", val);
+ if (ret == -EBUSY)
+ DRV_LOG(ERR, "Rules update timeout: 0x%08X", val);
+ else
+ DRV_LOG(ERR, "CSR poll failed, can't read value!");
return ret;
}
- DRV_LOG(DEBUG, "Rules update took %d cycles", ret);
if (mlx5_devx_regex_register_read(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
&val)) {
DRV_LOG(ERR, "CSR read failed!");
@@ -215,7 +219,7 @@
val &= ~(MLX5_RXP_RTRU_CSR_CTRL_GO);
if (mlx5_devx_regex_register_write(ctx, id, MLX5_RXP_RTRU_CSR_CTRL,
val)) {
- DRV_LOG(ERR, "CSR write write failed!");
+ DRV_LOG(ERR, "CSR write failed!");
return -1;
}
--
1.8.3.1