From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 80496A00E6 for ; Tue, 19 Mar 2019 12:15:09 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4A6244C95; Tue, 19 Mar 2019 12:15:09 +0100 (CET) Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by dpdk.org (Postfix) with ESMTP id 6A6C22C30; Tue, 19 Mar 2019 12:15:04 +0100 (CET) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id E875C22219; Tue, 19 Mar 2019 07:15:03 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Tue, 19 Mar 2019 07:15:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=Y1y8sg+xGV5dJpARoqE/Ow3eHah3S12hGRbVHB/8xtc=; b=Qf1yNwbWwFf2 wgvBujROpg0YG4Fc9L/fpi/MDbmdv0g9updcfyl2XBy939To/5+/UP5oori5WeTC mchWpkaMR2J5I8VHg/mhJ9YK5Qxsb3CQDu5ia5E/04ATS7nGRaSigE+JblP1DRMI /itYL/jKx/2EUgJ7RMqFk2JpK2LIj00= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=Y1y8sg+xGV5dJpARoqE/Ow3eHah3S12hGRbVHB/8x tc=; b=z8ZbyybQab3xiZg2HUH3JjV+GkP+iF79MJe3MysVmJDTukKoXwkoME4zk LMag115UCBI4QNzLocQVrxQhsEUIRibd+eTNS8PF3DUH53qTtX+cw62zj6BfA4RR 4LpTQA7bo4sMQFc2UMWywISQo+FOiDJ5xhFEdoivIJ6XZ0jUwvGcvJpfzWg1qZh5 sxFL2KqIHcP2z0vXLZXPXdyXI0Fdi2Hbmo1K3WMj0NecV7i3dCo4b+pc8xEUn5yC CutpjAbSMq1MXabpTd4RQGw7+i433R7o7IhQsyefayX4+pXGQHZEiIkwMahvqqn5 ulNSlvmDsSN+C8uTWlI5R1wDCiRQA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedutddrieeggddviecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkjghfggfgtgesthhqredttddtudenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucffoh hmrghinhepohhuthhlohhokhdrtghomhdpgedtmhgvlhhlrghnohigrdgtohhmnecukfhp peejjedrudefgedrvddtfedrudekgeenucfrrghrrghmpehmrghilhhfrhhomhepthhhoh hmrghssehmohhnjhgrlhhonhdrnhgvthenucevlhhushhtvghrufhiiigvpedt X-ME-Proxy: Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id 2F865E4580; Tue, 19 Mar 2019 07:15:01 -0400 (EDT) From: Thomas Monjalon To: Dekel Peled , Chao Zhu Cc: Yongseok Koh , Shahaf Shuler , "dev@dpdk.org" , Ori Kam , "stable@dpdk.org" Date: Tue, 19 Mar 2019 12:14:59 +0100 Message-ID: <1789153.zrlSK8XYcq@xps> In-Reply-To: References: <1552913893-43407-1-git-send-email-dekelp@mellanox.com> <001d01d4de03$378f18a0$a6ad49e0$@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" Subject: Re: [dpdk-stable] [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Guys, please let's avoid top-post. You are both not replying to each other: 1/ Dekel mentioned the IBM doc but Chao did not argue about the lack of IO protection with lwsync. We assume that rte_mb should protect any access including IO. 2/ Chao asked about the semantic of the barrier used in mlx5 code, but Dekel did not reply about the semantic: are we protecting IO or general memory access? 19/03/2019 11:05, Dekel Peled: > Hi, >=20 > For ppc, rte_io_mb() is defined as rte_mb(), which is defined as asm sync. > According to comments in arch/ppc_64/rte_atomic.h, rte_wmb() and rte_rmb(= ) are the same as rte_mb(), for store and load respectively. > My patch propose to define rte_wmb() and rte_rmb() as asm sync, like rte_= mb(), since using lwsync is incorrect for them. >=20 > Regards, > Dekel >=20 > > -----Original Message----- > > From: Chao Zhu > > Sent: Tuesday, March 19, 2019 5:24 AM > > To: Dekel Peled > > Cc: Yongseok Koh ; Shahaf Shuler > > ; dev@dpdk.org; Ori Kam ; > > Thomas Monjalon ; stable@dpdk.org > > Subject: RE: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER > >=20 > > Dekel=A3=AC > >=20 > > To control the memory order for device memory, I think you should use > > rte_io_mb() instead of rte_mb(). This will generate correct result. rte= _wmb() > > is used for system memory. > >=20 > > > -----Original Message----- > > > From: Dekel Peled > > > Sent: Monday, March 18, 2019 8:58 PM > > > To: chaozhu@linux.vnet.ibm.com > > > Cc: yskoh@mellanox.com; shahafs@mellanox.com; dev@dpdk.org; > > > orika@mellanox.com; thomas@monjalon.net; dekelp@mellanox.com; > > > stable@dpdk.org > > > Subject: [PATCH] eal/ppc: remove fix of memory barrier for IBM POWER > > > > > > From previous patch description: "to improve performance on PPC64, use > > > light weight sync instruction instead of sync instruction." > > > > > > Excerpt from IBM doc [1], section "Memory barrier instructions": > > > "The second form of the sync instruction is light-weight sync, or lws= ync. > > > This form is used to control ordering for storage accesses to system > > > memory only. It does not create a memory barrier for accesses to devi= ce > > memory." > > > > > > This patch removes the use of lwsync, so calls to rte_wmb() and > > > rte_rmb() will provide correct memory barrier to ensure order of > > > accesses to system memory and device memory. > > > > > > [1] > > > > > https://eur03.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fwww > > . > > > > > ibm.com%2Fdeveloperworks%2Fsystems%2Farticles%2Fpowerpc.html& > > ;data=3D > > > > > 02%7C01%7Cdekelp%40mellanox.com%7C381426b6b9d042f776fa08d6ac1a5d > > c5%7Ca > > > > > 652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636885626593364016&am > > p;sdata > > > > > =3DwFYTcFX2A%2BMdtQMgtojTAtUOzqds7U5pypNS%2F2SoXUM%3D&re > > served=3D0 > > > > > > Fixes: d23a6bd04d72 ("eal/ppc: fix memory barrier for IBM POWER") > > > Cc: stable@dpdk.org > > > > > > Signed-off-by: Dekel Peled > > > --- > > > lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h | 8 -------- > > > 1 file changed, 8 deletions(-) > > > > > > diff --git a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > > > b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > > > index ce38350..797381c 100644 > > > --- a/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > > > +++ b/lib/librte_eal/common/include/arch/ppc_64/rte_atomic.h > > > @@ -63,11 +63,7 @@ > > > * Guarantees that the STORE operations generated before the barrier > > > * occur before the STORE operations generated after. > > > */ > > > -#ifdef RTE_ARCH_64 > > > -#define rte_wmb() asm volatile("lwsync" : : : "memory") > > > -#else > > > #define rte_wmb() asm volatile("sync" : : : "memory") > > > -#endif > > > > > > /** > > > * Read memory barrier. > > > @@ -75,11 +71,7 @@ > > > * Guarantees that the LOAD operations generated before the barrier > > > * occur before the LOAD operations generated after. > > > */ > > > -#ifdef RTE_ARCH_64 > > > -#define rte_rmb() asm volatile("lwsync" : : : "memory") > > > -#else > > > #define rte_rmb() asm volatile("sync" : : : "memory") > > > -#endif > > > > > > #define rte_smp_mb() rte_mb()