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Thu, 20 Dec 2018 00:02:35 +0000 From: Yongseok Koh To: Rasesh Mody CC: "Mody, Rasesh" , "stable@dpdk.org" , "Shaikh, Shahed" , Dept-Eng DPDK Dev Thread-Topic: [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow Thread-Index: AQHUlzO6BJhUXNxlvU6aeBEQAlJSm6WGfxSAgAAifyCAAB6jAA== Date: Thu, 20 Dec 2018 00:02:35 +0000 Message-ID: <1DDBC7A8-C85B-4B76-BDDD-8719023D37A2@mellanox.com> References: <1545180127-3202-1-git-send-email-rasesh.mody@cavium.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-originating-ip: [69.181.245.183] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB3PR0502MB4012; 6:I28tGTsZDM+JXATyMMlSiw2wxOmLwsqRIDYet32MbTbVRSPd4x47jzKmZ/nsRjnMlZlrIISEPhsTwO4PTYmW/ESzepprSI7x7dD7ITzvsUcHtsRmIAAoFD3tshC0GOrZPALvhmibmijFBz8iHhSW1m+DfXA4D95MNtD5ZMMI+kmYdXFH974IxYqkIJs7qL73HSLlbu8hPKAmyh7F7eHI72g0yzdd7PGLYzB1tjtU4juqQiXbdWuzjNkF6wyrtio+uOfoTgu8K85pG8MuDfamQozGDdU87Fg/SJvDsYGGrnFksBP78RujY1dZlxjgaAOVDeL1bq1SLBDlebJ0/6pntaJaEl/vvKsQaGWUH0zDzcLz20DCEZ9xVBGcJ1wS/n5BtVG9WGkYzCjrs5Ku9Gf4XpzSyWHXaQbsusKYers3l08AbcS8tYrALHvr4ab4w59tc6omy41uEa8UpjQNsG7u6A==; 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charset="us-ascii" Content-ID: <62421662BFEE5A4C8F63A249E0DC821A@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4c74a76c-eaff-42f4-658e-08d6660e7274 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Dec 2018 00:02:35.4528 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4012 Subject: Re: [dpdk-stable] [PATCH 17.11 1/5] net/qede/base: fix MFW FLR flow X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Dec 2018 00:02:37 -0000 > On Dec 19, 2018, at 2:18 PM, Rasesh Mody wrote: >=20 >> From: Yongseok Koh >> Sent: Wednesday, December 19, 2018 12:09 PM >>=20 >>> On Dec 18, 2018, at 4:42 PM, Mody, Rasesh >> wrote: >>>=20 >>> From: Shahed Shaikh >>>=20 >>> [ backported from upstream commit >>> 797ce8eec7c1b9e37dd9398403e9bc888cca0013 ] >>>=20 >>> Management firmware does not properly clean IGU block in PF FLR flow >>> which may result in undelivered attentions for link events from >>> default status block. >>> Add a workaround in PMD to execute extra IGU cleanup right after PF >>> FLR is done. >>>=20 >>> Fixes: 9e2f08a4ad5f ("net/qede/base: add request for PF FLR before >>> load request") >>>=20 >>> Signed-off-by: Shahed Shaikh >>=20 >> Thanks, I was waiting for patches from you. :-) >>=20 >> Series applied to stable/18.11 >=20 > Thanks, you mean stable/17.11, right? Right, that was a typo. :-) Yongseok >>=20 >>> --- >>> drivers/net/qede/base/ecore_dev.c | 7 +++++++ >>> drivers/net/qede/base/ecore_int.c | 32 >> ++++++++++++++++++++++++++++++++ >>> drivers/net/qede/base/ecore_int.h | 1 + >>> drivers/net/qede/base/mcp_public.h | 2 ++ >>> drivers/net/qede/base/reg_addr.h | 15 +++++++++++++++ >>> 5 files changed, 57 insertions(+) >>>=20 >>> diff --git a/drivers/net/qede/base/ecore_dev.c >>> b/drivers/net/qede/base/ecore_dev.c >>> index 092606b..6a3046d 100644 >>> --- a/drivers/net/qede/base/ecore_dev.c >>> +++ b/drivers/net/qede/base/ecore_dev.c >>> @@ -4096,6 +4096,13 @@ void ecore_prepare_hibernate(struct ecore_dev >> *p_dev) >>> rc =3D ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_pt= t); >>> if (rc !=3D ECORE_SUCCESS) >>> DP_NOTICE(p_hwfn, false, "Failed to initiate PF >>> FLR\n"); >>> + >>> + /* Workaround for MFW issue where PF FLR does not cleanup >>> + * IGU block >>> + */ >>> + if (!(p_hwfn->mcp_info->capabilities & >>> + FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP)) >>> + ecore_pf_flr_igu_cleanup(p_hwfn); >>> } >>>=20 >>> /* Check if mdump logs/data are present and update the epoch >>> value */ diff --git a/drivers/net/qede/base/ecore_int.c >>> b/drivers/net/qede/base/ecore_int.c >>> index 61e36a4..b2582aa 100644 >>> --- a/drivers/net/qede/base/ecore_int.c >>> +++ b/drivers/net/qede/base/ecore_int.c >>> @@ -2679,3 +2679,35 @@ enum _ecore_status_t >>> ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn, >>>=20 >>> return ECORE_SUCCESS; >>> } >>> + >>> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn) { >>> + struct ecore_ptt *p_ptt =3D p_hwfn->p_main_ptt; >>> + struct ecore_ptt *p_dpc_ptt =3D ecore_get_reserved_ptt(p_hwfn, >>> + RESERVED_PTT= _DPC); >>> + int i; >>> + >>> + /* Do not reorder the following cleanup sequence */ >>> + /* Ack all attentions */ >>> + ecore_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ACK_BITS, 0xfff); >>> + >>> + /* Clear driver attention */ >>> + ecore_wr(p_hwfn, p_dpc_ptt, >>> + ((p_hwfn->rel_pf_id << 3) + >>> + MISC_REG_AEU_GENERAL_ATTN_0), 0); >>> + >>> + /* Clear per-PF IGU registers to restore them as if the IGU >>> + * was reset for this PF >>> + */ >>> + ecore_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); >>> + ecore_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); >>> + ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); >>> + >>> + /* Execute IGU clean up*/ >>> + ecore_wr(p_hwfn, p_ptt, IGU_REG_PF_FUNCTIONAL_CLEANUP, 1); >>> + >>> + /* Clear Stats */ >>> + ecore_wr(p_hwfn, p_ptt, >> IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED, >>> + 0); >>> + >>> + for (i =3D 0; i < IGU_REG_PBA_STS_PF_SIZE; i++) >>> + ecore_wr(p_hwfn, p_ptt, IGU_REG_PBA_STS_PF + i * 4, 0); >>> +} >>> diff --git a/drivers/net/qede/base/ecore_int.h >>> b/drivers/net/qede/base/ecore_int.h >>> index 563051c..ebee68b 100644 >>> --- a/drivers/net/qede/base/ecore_int.h >>> +++ b/drivers/net/qede/base/ecore_int.h >>> @@ -258,4 +258,5 @@ enum _ecore_status_t >>> ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn, enum >> _ecore_status_t ecore_pglueb_rbc_attn_handler(struct ecore_hwfn >> *p_hwfn, >>> struct ecore_ptt >>> *p_ptt); >>>=20 >>> +void ecore_pf_flr_igu_cleanup(struct ecore_hwfn *p_hwfn); >>> #endif /* __ECORE_INT_H__ */ >>> diff --git a/drivers/net/qede/base/mcp_public.h >>> b/drivers/net/qede/base/mcp_public.h >>> index 81ca663..b83b241 100644 >>> --- a/drivers/net/qede/base/mcp_public.h >>> +++ b/drivers/net/qede/base/mcp_public.h >>> @@ -1777,6 +1777,8 @@ struct public_drv_mb { >>> #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 >>> /* MFW supports EEE */ >>> #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 >>> +/* MFW support complete IGU cleanup upon FLR */ >>> +#define FW_MB_PARAM_FEATURE_SUPPORT_IGU_CLEANUP >> 0x00000080 >>> /* MFW supports virtual link */ >>> #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 >>>=20 >>> diff --git a/drivers/net/qede/base/reg_addr.h >>> b/drivers/net/qede/base/reg_addr.h >>> index ad15d28..8f226ad 100644 >>> --- a/drivers/net/qede/base/reg_addr.h >>> +++ b/drivers/net/qede/base/reg_addr.h >>> @@ -332,6 +332,21 @@ >>> 0x180820UL >>> #define IGU_REG_ATTN_MSG_ADDR_H \ >>> 0x180824UL >>> +#define IGU_REG_LEADING_EDGE_LATCH \ >>> + 0x18082cUL >>> +#define IGU_REG_TRAILING_EDGE_LATCH \ >>> + 0x180830UL >>> +#define IGU_REG_ATTENTION_ACK_BITS \ >>> + 0x180838UL >>> +#define IGU_REG_PBA_STS_PF \ >>> + 0x180d20UL >>> +#define IGU_REG_PF_FUNCTIONAL_CLEANUP \ >>> + 0x181210UL >>> +#define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED \ >>> + 0x18042cUL >>> +#define IGU_REG_PBA_STS_PF_SIZE 5 >>> +#define IGU_REG_PBA_STS_PF \ >>> + 0x180d20UL >>> #define MISC_REG_AEU_GENERAL_ATTN_0 \ >>> 0x008400UL >>> #define CAU_REG_SB_ADDR_MEMORY \ >>> -- >>> 1.7.10.3