From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by dpdk.org (Postfix) with ESMTP id 9E459378E for ; Fri, 27 Jul 2018 12:18:11 +0200 (CEST) Received: by mail-wr1-f68.google.com with SMTP id c13-v6so4521247wrt.1 for ; Fri, 27 Jul 2018 03:18:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zDHsvxwAOhVvPPGRvV37X4m0GcaolYgrRwt9W/lzk9g=; b=gHaPUPYVBVPfeGcVDu3yMmaDmKGCQCgQEXWJLh0ZMl2wB+cuIzWC3HH6C+kD/KVYHB EOS34r+710J5MdxydyK7kQbVe80bV/wjxOfj9WCZpwsjPlwfpue2IMRsrEktbObAUWCb gtPgpVrbexxyUK3aUH2MUqVBjZiw6KA58z1xf0VSv4IQbDugtxPRiqIQgWkbjmLTqaLg LmwZzfUGCEeXscf7Q1dY8ANbgVKIZDGeGNAYVnzUO/MAa+wOrVZVTeJKPc1IhJD9YMT9 WJukUCz/A1OlmsNZmExAibZpvQCk9CBE5Jr1TGf8pGtWun+H1rbiB8nUyYPjt3CcbNEm Llyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zDHsvxwAOhVvPPGRvV37X4m0GcaolYgrRwt9W/lzk9g=; b=d5VMN7SRH1Zo9aW7UD96x5JMAAMlf4NIFj2yVjZ4uNupKTkfISnfkfKEQQJlxp15BJ hYeTGNP6gm4mIHsOM2j3/JsHETo0Y4bFeFUq9IQxjCl6GnV9qlJ37YgyDgx7NDLT542U sFrcM05RPNeNmMEo3MRm+dLjUzGAESDR/gMRhQDoBY2bNVYZo2ae1tZStpv+LYgA2t7L yQEGlHp7WXt/Q4vkl3xK2dV5WsBjMWe5F4XChxbwvd6RYiXRd+LK+zeeNOyb5NXx4D03 m4fc2j8ymKq4vaSy9bsY0DR6SpvtUQpDy/o5eMkSV0HvPe+0/VSOyfYNFIPYvrEVMcWH LkiA== X-Gm-Message-State: AOUpUlHOfyifLQQ044EVdCO5Bp5rUhMdkAXighgBx1tjW4OhcJt93vNZ N/higxDLUVb+v7jm+z/SuwU= X-Google-Smtp-Source: AAOMgpd+lsvnXYWLZNEB/A+j+85lDdJwPDwj5l0QL1bRae+6UKk5kjIRRQSq/aWBr4CaBKgEk1w4AQ== X-Received: by 2002:adf:e50f:: with SMTP id j15-v6mr4317431wrm.111.1532686691403; Fri, 27 Jul 2018 03:18:11 -0700 (PDT) Received: from localhost ([2a00:23c5:be94:4600:7b12:f8a0:fd52:f87d]) by smtp.gmail.com with ESMTPSA id h14-v6sm2765615wro.15.2018.07.27.03.18.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Jul 2018 03:18:10 -0700 (PDT) From: luca.boccassi@gmail.com To: Pablo de Lara Cc: dpdk stable Date: Fri, 27 Jul 2018 11:17:46 +0100 Message-Id: <20180727101748.30228-10-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727101748.30228-1-luca.boccassi@gmail.com> References: <20180724160752.20287-34-luca.boccassi@gmail.com> <20180727101748.30228-1-luca.boccassi@gmail.com> Subject: [dpdk-stable] patch 'test/hash: fix multiwriter with non consecutive cores' has been queued to LTS release 16.11.8 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jul 2018 10:18:11 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.8 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 07/29/18. So please shout if anyone has objections. Thanks. Luca Boccassi --- >>From dc829c2fe2bcef723c3a3c5301aaf93f192042a1 Mon Sep 17 00:00:00 2001 From: Pablo de Lara Date: Tue, 17 Jul 2018 14:31:50 +0100 Subject: [PATCH] test/hash: fix multiwriter with non consecutive cores [ upstream commit 0c992822901464d440534d337838fd08acf233d4 ] When non consecutive cores are passed into the test application, the distribution of the keys that each thread needs to insert is not correct, since it assumes that there are no cores skipped between the master core and the worker core. Fixes: be856325cba3 ("hash: add scalable multi-writer insertion with Intel TSX") Signed-off-by: Pablo de Lara --- app/test/test_hash_multiwriter.c | 41 ++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/app/test/test_hash_multiwriter.c b/app/test/test_hash_multiwriter.c index 4dcbd9d56..951c3e743 100644 --- a/app/test/test_hash_multiwriter.c +++ b/app/test/test_hash_multiwriter.c @@ -76,18 +76,29 @@ static rte_atomic64_t ginsertions; static int use_htm; static int -test_hash_multiwriter_worker(__attribute__((unused)) void *arg) +test_hash_multiwriter_worker(void *arg) { uint64_t i, offset; + uint16_t pos_core; uint32_t lcore_id = rte_lcore_id(); uint64_t begin, cycles; + uint16_t *enabled_core_ids = (uint16_t *)arg; - offset = (lcore_id - rte_get_master_lcore()) - * tbl_multiwriter_test_params.nb_tsx_insertion; + for (pos_core = 0; pos_core < rte_lcore_count(); pos_core++) { + if (enabled_core_ids[pos_core] == lcore_id) + break; + } + + /* + * Calculate offset for entries based on the position of the + * logical core, from the master core (not counting not enabled cores) + */ + offset = pos_core * tbl_multiwriter_test_params.nb_tsx_insertion; printf("Core #%d inserting %d: %'"PRId64" - %'"PRId64"\n", lcore_id, tbl_multiwriter_test_params.nb_tsx_insertion, - offset, offset + tbl_multiwriter_test_params.nb_tsx_insertion); + offset, + offset + tbl_multiwriter_test_params.nb_tsx_insertion - 1); begin = rte_rdtsc_precise(); @@ -116,6 +127,8 @@ test_hash_multiwriter(void) { unsigned int i, rounded_nb_total_tsx_insertion; static unsigned calledCount = 1; + uint16_t enabled_core_ids[RTE_MAX_LCORE]; + uint16_t core_id; uint32_t *keys; uint32_t *found; @@ -186,9 +199,27 @@ test_hash_multiwriter(void) rte_atomic64_init(&ginsertions); rte_atomic64_clear(&ginsertions); + /* Get list of enabled cores */ + i = 0; + for (core_id = 0; core_id < RTE_MAX_LCORE; core_id++) { + if (i == rte_lcore_count()) + break; + + if (rte_lcore_is_enabled(core_id)) { + enabled_core_ids[i] = core_id; + i++; + } + } + + if (i != rte_lcore_count()) { + printf("Number of enabled cores in list is different from " + "number given by rte_lcore_count()\n"); + goto err3; + } + /* Fire all threads. */ rte_eal_mp_remote_launch(test_hash_multiwriter_worker, - NULL, CALL_MASTER); + enabled_core_ids, CALL_MASTER); rte_eal_mp_wait_lcore(); while (rte_hash_iterate(handle, &next_key, &next_data, &iter) >= 0) { -- 2.18.0