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From: Ferruh Yigit <ferruh.yigit@intel.com>
To: Konstantin Ananyev <konstantin.ananyev@intel.com>,
Jasvinder Singh <jasvinder.singh@intel.com>,
Olivier Matz <olivier.matz@6wind.com>
Cc: dev@dpdk.org,
Ferruh Yigit <ferruh.yigit@intel.com>,
stable@dpdk.org
Date: Sun, 28 Oct 2018 01:08:44 +0000
Message-Id: <20181028010846.81730-1-ferruh.yigit@intel.com>
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Subject: [dpdk-stable] [PATCH 1/3] lib: fix shifting 32 bits signed variable
31 times
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Fix cppcheck warning by marking variable as unsigned.
Fixes: dc276b5780c2 ("acl: new library")
Fixes: 986ff526fb84 ("net: add CRC computation API")
Cc: stable@dpdk.org
Signed-off-by: Ferruh Yigit <ferruh.yigit@intel.com>
---
lib/librte_acl/acl_gen.c | 2 +-
lib/librte_net/rte_net_crc.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/lib/librte_acl/acl_gen.c b/lib/librte_acl/acl_gen.c
index bed66be08..35a0140b4 100644
--- a/lib/librte_acl/acl_gen.c
+++ b/lib/librte_acl/acl_gen.c
@@ -163,7 +163,7 @@ acl_count_sequential_groups(struct rte_acl_bitset *bits, int zero_one)
for (n = QRANGE_MIN; n < UINT8_MAX + 1; n++) {
if (bits->bits[n / (sizeof(bits_t) * 8)] &
- (1 << (n % (sizeof(bits_t) * 8)))) {
+ (1U << (n % (sizeof(bits_t) * 8)))) {
if (zero_one == 1 && last_bit != 1)
ranges++;
last_bit = 1;
diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c
index 73ac3a959..dca0830e2 100644
--- a/lib/librte_net/rte_net_crc.c
+++ b/lib/librte_net/rte_net_crc.c
@@ -69,8 +69,8 @@ reflect_32bits(uint32_t val)
uint32_t i, res = 0;
for (i = 0; i < 32; i++)
- if ((val & (1 << i)) != 0)
- res |= (uint32_t)(1 << (31 - i));
+ if ((val & (1U << i)) != 0)
+ res |= (uint32_t)(1U << (31 - i));
return res;
}
--
2.17.2