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From: Kevin Traynor <ktraynor@redhat.com>
To: Gavin Hu <gavin.hu@arm.com>
Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>,
Steve Capper <steve.capper@arm.com>, Ola Liljedahl <ola.liljedahl@arm.com>,
Jia He <justin.he@arm.com>, Jerin Jacob <jerin.jacob@caviumnetworks.com>,
Olivier Matz <olivier.matz@6wind.com>, dpdk stable <stable@dpdk.org>
Date: Fri, 23 Nov 2018 10:26:30 +0000
Message-Id: <20181123102713.17309-26-ktraynor@redhat.com>
In-Reply-To: <20181123102713.17309-1-ktraynor@redhat.com>
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(mx1.redhat.com [10.5.110.49]); Fri, 23 Nov 2018 10:29:26 +0000 (UTC)
Subject: [dpdk-stable] patch 'ring/c11: synchronize load and store of the
tail' has been queued to stable release 18.08.1
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Hi,
FYI, your patch has been queued to stable release 18.08.1
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/29/18. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the patch applied
to the branch. If the code is different (ie: not only metadata diffs), due for example to
a change in context or macro names, please double check it.
Thanks.
Kevin Traynor
---
>>From f57da12160802dfe41ef7b82c7d41316769d9179 Mon Sep 17 00:00:00 2001
From: Gavin Hu <gavin.hu@arm.com>
Date: Fri, 2 Nov 2018 19:21:27 +0800
Subject: [PATCH] ring/c11: synchronize load and store of the tail
[ upstream commit 9ed877062898dd1eb7150bca56ebbd5329e96ee4 ]
Synchronize the load-acquire of the tail and the store-release
within update_tail, the store release ensures all the ring operations,
enqueue or dequeue, are seen by the observers on the other side as soon
as they see the updated tail. The load-acquire is needed here as the
data dependency is not a reliable way for ordering as the compiler might
break it by saving to temporary values to boost performance.
When computing the free_entries and avail_entries, use atomic semantics
to load the heads and tails instead.
The patch was benchmarked with test/ring_perf_autotest and it decreases
the enqueue/dequeue latency by 5% ~ 27.6% with two lcores, the real gains
are dependent on the number of lcores, depth of the ring, SPSC or MPMC.
For 1 lcore, it also improves a little, about 3 ~ 4%.
It is a big improvement, in case of MPMC, with two lcores and ring size
of 32, it saves latency up to (3.26-2.36)/3.26 = 27.6%.
This patch is a bug fix, while the improvement is a bonus. In our analysis
the improvement comes from the cacheline pre-filling after hoisting load-
acquire from _atomic_compare_exchange_n up above.
The test command:
$sudo ./test/test/test -l 16-19,44-47,72-75,100-103 -n 4 --socket-mem=\
1024 -- -i
Test result with this patch(two cores):
SP/SC bulk enq/dequeue (size: 8): 5.86
MP/MC bulk enq/dequeue (size: 8): 10.15
SP/SC bulk enq/dequeue (size: 32): 1.94
MP/MC bulk enq/dequeue (size: 32): 2.36
In comparison of the test result without this patch:
SP/SC bulk enq/dequeue (size: 8): 6.67
MP/MC bulk enq/dequeue (size: 8): 13.12
SP/SC bulk enq/dequeue (size: 32): 2.04
MP/MC bulk enq/dequeue (size: 32): 3.26
Fixes: 39368ebfc6 ("ring: introduce C11 memory model barrier option")
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Ola Liljedahl <ola.liljedahl@arm.com>
Reviewed-by: Jia He <justin.he@arm.com>
Acked-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Tested-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
Acked-by: Olivier Matz <olivier.matz@6wind.com>
---
lib/librte_ring/rte_ring_c11_mem.h | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/lib/librte_ring/rte_ring_c11_mem.h b/lib/librte_ring/rte_ring_c11_mem.h
index 94df3c4a6..52da95a21 100644
--- a/lib/librte_ring/rte_ring_c11_mem.h
+++ b/lib/librte_ring/rte_ring_c11_mem.h
@@ -58,4 +58,5 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,
{
const uint32_t capacity = r->capacity;
+ uint32_t cons_tail;
unsigned int max = n;
int success;
@@ -68,11 +69,16 @@ __rte_ring_move_prod_head(struct rte_ring *r, unsigned int is_sp,
__ATOMIC_ACQUIRE);
- /*
- * The subtraction is done between two unsigned 32bits value
+ /* load-acquire synchronize with store-release of ht->tail
+ * in update_tail.
+ */
+ cons_tail = __atomic_load_n(&r->cons.tail,
+ __ATOMIC_ACQUIRE);
+
+ /* The subtraction is done between two unsigned 32bits value
* (the result is always modulo 32 bits even if we have
* *old_head > cons_tail). So 'free_entries' is always between 0
* and capacity (which is < size).
*/
- *free_entries = (capacity + r->cons.tail - *old_head);
+ *free_entries = (capacity + cons_tail - *old_head);
/* check that we have enough room in ring */
@@ -126,4 +132,5 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
{
unsigned int max = n;
+ uint32_t prod_tail;
int success;
@@ -132,7 +139,14 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
/* Restore n as it may change every loop */
n = max;
+
*old_head = __atomic_load_n(&r->cons.head,
__ATOMIC_ACQUIRE);
+ /* this load-acquire synchronize with store-release of ht->tail
+ * in update_tail.
+ */
+ prod_tail = __atomic_load_n(&r->prod.tail,
+ __ATOMIC_ACQUIRE);
+
/* The subtraction is done between two unsigned 32bits value
* (the result is always modulo 32 bits even if we have
@@ -140,5 +154,5 @@ __rte_ring_move_cons_head(struct rte_ring *r, int is_sc,
* and size(ring)-1.
*/
- *entries = (r->prod.tail - *old_head);
+ *entries = (prod_tail - *old_head);
/* Set the actual entries for dequeue */
--
2.19.0
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2018-11-23 10:22:54.936963738 +0000
+++ 0026-ring-c11-synchronize-load-and-store-of-the-tail.patch 2018-11-23 10:22:54.000000000 +0000
@@ -1,8 +1,10 @@
-From 9ed877062898dd1eb7150bca56ebbd5329e96ee4 Mon Sep 17 00:00:00 2001
+From f57da12160802dfe41ef7b82c7d41316769d9179 Mon Sep 17 00:00:00 2001
From: Gavin Hu <gavin.hu@arm.com>
Date: Fri, 2 Nov 2018 19:21:27 +0800
Subject: [PATCH] ring/c11: synchronize load and store of the tail
+[ upstream commit 9ed877062898dd1eb7150bca56ebbd5329e96ee4 ]
+
Synchronize the load-acquire of the tail and the store-release
within update_tail, the store release ensures all the ring operations,
enqueue or dequeue, are seen by the observers on the other side as soon
@@ -40,7 +42,6 @@
MP/MC bulk enq/dequeue (size: 32): 3.26
Fixes: 39368ebfc6 ("ring: introduce C11 memory model barrier option")
-Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>