From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by dpdk.org (Postfix) with ESMTP id 6F4F01B615 for ; Mon, 26 Nov 2018 13:49:29 +0100 (CET) Received: by mail-wr1-f65.google.com with SMTP id x10so18771076wrs.8 for ; Mon, 26 Nov 2018 04:49:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+cIALVLXnkmj5A1O0JiGT+3xa43rEGPiAsef5KFaScY=; b=Od9L3pRtwlvVKZhGP+EjkJqYpSD2izWjihUE0qWx+eUmswytBmc0LyowkFf+KYwCiW Plk0abEihhcuR9EM/UyNUidAB2naZXGrStassWaSRLzwfmTKYpLXEbuADqR2yzB98Cr7 2yqtd7WkptvhznC72tsGF4MTI3SNv3a4NGhwxA8my+594WlVXZ1dcKMG7K+cnlTZB+46 GJeqivjQRsOyqAn0fmA/Nr/OqKbR1u+mDTMaW1YSsQRoaVfbopxxFqpxe7dCVhV1X/1H o7MoxTAedih3lE6yWcjzj9Sw0d0+hPay9IU8k5qpGugY1UxDAB62yQ7KUhp+SI/892Ck hlkw== X-Gm-Message-State: AA+aEWYU59JVJYnaa1HDqmB1vv6jxUTG5qCSCwEF3vqI7bpFeCqBsIyF UJaD1464ySN1jc9Yz8VFyFA= X-Google-Smtp-Source: AFSGD/WS1AhsKk6R3f84zaC3X3YT8hgdoBG+xos3tonMc1nToyZzt35kMuSwJHlFDI6LgL1aopYiDw== X-Received: by 2002:adf:dbcb:: with SMTP id e11mr20928734wrj.58.1543236569006; Mon, 26 Nov 2018 04:49:29 -0800 (PST) Received: from localhost ([2a01:4b00:f419:6f00:8361:8946:ba2b:d556]) by smtp.gmail.com with ESMTPSA id x15sm299812wrs.27.2018.11.26.04.49.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Nov 2018 04:49:27 -0800 (PST) From: Luca Boccassi To: Yanglong Wu Cc: Qi Zhang , dpdk stable Date: Mon, 26 Nov 2018 12:49:15 +0000 Message-Id: <20181126124916.16240-4-bluca@debian.org> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181126124916.16240-1-bluca@debian.org> References: <20181119122538.14207-1-bluca@debian.org> <20181126124916.16240-1-bluca@debian.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] patch 'net/ixgbe: fix TDH register write' has been queued to LTS release 16.11.9 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Nov 2018 12:49:29 -0000 Hi, FYI, your patch has been queued to LTS release 16.11.9 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/28/18. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. If the code is different (ie: not only metadata diffs), due for example to a change in context or macro names, please double check it. Thanks. Luca Boccassi --- >>From 959bee3ddbf0ebec8248dd7fd4e62f4a37aedc0b Mon Sep 17 00:00:00 2001 From: Yanglong Wu Date: Tue, 20 Nov 2018 13:59:21 +0800 Subject: [PATCH] net/ixgbe: fix TDH register write [ upstream commit ff30a020bb400f04bf64a91416993862f45f9ada ] The only time that software should write to the TDH register is after a reset (hardware reset or CTRL.RST) and before enabling the transmit function (TXDCTL.ENABLE). If software were to write to this register while the transmit function was enabled, the on-chip descriptor buffers might be invalidated and the hardware could become confused. Fixes: 029fd06d40fa ("ixgbe: queue start and stop") Signed-off-by: Yanglong Wu Acked-by: Qi Zhang --- drivers/net/ixgbe/ixgbe_rxtx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c index 55afb5393..4b1a6f48e 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c @@ -5000,6 +5000,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) if (tx_queue_id < dev->data->nb_tx_queues) { txq = dev->data->tx_queues[tx_queue_id]; + IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); txdctl |= IXGBE_TXDCTL_ENABLE; IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); @@ -5017,7 +5018,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) "Tx Queue %d", tx_queue_id); } rte_wmb(); - IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; } else -- 2.19.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2018-11-26 12:45:13.687842423 +0000 +++ 0004-net-ixgbe-fix-TDH-register-write.patch 2018-11-26 12:45:13.611202330 +0000 @@ -1,8 +1,10 @@ -From ff30a020bb400f04bf64a91416993862f45f9ada Mon Sep 17 00:00:00 2001 +From 959bee3ddbf0ebec8248dd7fd4e62f4a37aedc0b Mon Sep 17 00:00:00 2001 From: Yanglong Wu Date: Tue, 20 Nov 2018 13:59:21 +0800 Subject: [PATCH] net/ixgbe: fix TDH register write +[ upstream commit ff30a020bb400f04bf64a91416993862f45f9ada ] + The only time that software should write to the TDH register is after a reset (hardware reset or CTRL.RST) and before enabling the transmit function (TXDCTL.ENABLE). @@ -11,7 +13,6 @@ be invalidated and the hardware could become confused. Fixes: 029fd06d40fa ("ixgbe: queue start and stop") -Cc: stable@dpdk.org Signed-off-by: Yanglong Wu Acked-by: Qi Zhang @@ -20,25 +21,25 @@ 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c -index 2f0262ae1..ddc7efa87 100644 +index 55afb5393..4b1a6f48e 100644 --- a/drivers/net/ixgbe/ixgbe_rxtx.c +++ b/drivers/net/ixgbe/ixgbe_rxtx.c -@@ -5264,6 +5264,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) - hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); - - txq = dev->data->tx_queues[tx_queue_id]; -+ IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); - txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); - txdctl |= IXGBE_TXDCTL_ENABLE; - IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); -@@ -5281,7 +5282,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) - tx_queue_id); - } - rte_wmb(); -- IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); - IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); - dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; +@@ -5000,6 +5000,7 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) + if (tx_queue_id < dev->data->nb_tx_queues) { + txq = dev->data->tx_queues[tx_queue_id]; ++ IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); + txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(txq->reg_idx)); + txdctl |= IXGBE_TXDCTL_ENABLE; + IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(txq->reg_idx), txdctl); +@@ -5017,7 +5018,6 @@ ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id) + "Tx Queue %d", tx_queue_id); + } + rte_wmb(); +- IXGBE_WRITE_REG(hw, IXGBE_TDH(txq->reg_idx), 0); + IXGBE_WRITE_REG(hw, IXGBE_TDT(txq->reg_idx), 0); + dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; + } else -- 2.19.2