From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id A6BB91B4BA for ; Thu, 29 Nov 2018 14:23:22 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 16D4E308FBB1; Thu, 29 Nov 2018 13:23:22 +0000 (UTC) Received: from ktraynor.remote.csb (ovpn-117-230.ams2.redhat.com [10.36.117.230]) by smtp.corp.redhat.com (Postfix) with ESMTP id AE3C71019626; Thu, 29 Nov 2018 13:23:20 +0000 (UTC) From: Kevin Traynor To: Yongseok Koh Cc: Shahaf Shuler , dpdk stable Date: Thu, 29 Nov 2018 13:20:49 +0000 Message-Id: <20181129132128.7609-49-ktraynor@redhat.com> In-Reply-To: <20181129132128.7609-1-ktraynor@redhat.com> References: <20181129132128.7609-1-ktraynor@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Thu, 29 Nov 2018 13:23:22 +0000 (UTC) Subject: [dpdk-stable] patch 'net/mlx5: optimize Tx doorbell write' has been queued to stable release 18.08.1 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Nov 2018 13:23:23 -0000 Hi, FYI, your patch has been queued to stable release 18.08.1 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/08/18. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. If the code is different (ie: not only metadata diffs), due for example to a change in context or macro names, please double check it. Thanks. Kevin Traynor --- >>From 25edba0ea0a2262fd8b6efd3fa80b4060ead29f6 Mon Sep 17 00:00:00 2001 From: Yongseok Koh Date: Thu, 15 Nov 2018 10:29:19 +0000 Subject: [PATCH] net/mlx5: optimize Tx doorbell write [ upstream commit 317e64739de05a67406f43dd1860433359a81435 ] Unnecessary volatile attribute keeps compiler from further optimizing the code and this results in a little performance drop (~2%). Because of memory barriers, it is safe to remove. Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems") Signed-off-by: Yongseok Koh Acked-by: Shahaf Shuler --- drivers/net/mlx5/mlx5_rxtx.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index e1dc6db21..d06e1e795 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -379,15 +379,14 @@ uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr, */ static __rte_always_inline void -__mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr, +__mlx5_uar_write64_relaxed(uint64_t val, void *addr, rte_spinlock_t *lock __rte_unused) { #ifdef RTE_ARCH_64 - rte_write64_relaxed(val, addr); + *(uint64_t *)addr = val; #else /* !RTE_ARCH_64 */ rte_spinlock_lock(lock); - rte_write32_relaxed(val, addr); + *(uint32_t *)addr = val; rte_io_wmb(); - rte_write32_relaxed(val >> 32, - (volatile void *)((volatile char *)addr + 4)); + *((uint32_t *)addr + 1) = val >> 32; rte_spinlock_unlock(lock); #endif @@ -407,5 +406,5 @@ __mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr, */ static __rte_always_inline void -__mlx5_uar_write64(uint64_t val, volatile void *addr, rte_spinlock_t *lock) +__mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) { rte_io_wmb(); -- 2.19.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2018-11-29 13:11:36.294946977 +0000 +++ 0048-net-mlx5-optimize-Tx-doorbell-write.patch 2018-11-29 13:11:34.000000000 +0000 @@ -1,14 +1,15 @@ -From 317e64739de05a67406f43dd1860433359a81435 Mon Sep 17 00:00:00 2001 +From 25edba0ea0a2262fd8b6efd3fa80b4060ead29f6 Mon Sep 17 00:00:00 2001 From: Yongseok Koh Date: Thu, 15 Nov 2018 10:29:19 +0000 Subject: [PATCH] net/mlx5: optimize Tx doorbell write +[ upstream commit 317e64739de05a67406f43dd1860433359a81435 ] + Unnecessary volatile attribute keeps compiler from further optimizing the code and this results in a little performance drop (~2%). Because of memory barriers, it is safe to remove. Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems") -Cc: stable@dpdk.org Signed-off-by: Yongseok Koh Acked-by: Shahaf Shuler @@ -17,10 +18,10 @@ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h -index 59fb43fef..e210453fe 100644 +index e1dc6db21..d06e1e795 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h -@@ -380,15 +380,14 @@ uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr, +@@ -379,15 +379,14 @@ uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr, */ static __rte_always_inline void -__mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr, @@ -40,7 +41,7 @@ + *((uint32_t *)addr + 1) = val >> 32; rte_spinlock_unlock(lock); #endif -@@ -408,5 +407,5 @@ __mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr, +@@ -407,5 +406,5 @@ __mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr, */ static __rte_always_inline void -__mlx5_uar_write64(uint64_t val, volatile void *addr, rte_spinlock_t *lock)