From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id AE5A2A0096 for ; Fri, 15 Mar 2019 20:09:19 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 456AF1E2F; Fri, 15 Mar 2019 20:09:18 +0100 (CET) Received: from NAM01-SN1-obe.outbound.protection.outlook.com (mail-eopbgr820103.outbound.protection.outlook.com [40.107.82.103]) by dpdk.org (Postfix) with ESMTP id 368BB1E2F for ; Fri, 15 Mar 2019 20:09:17 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=spirent1.onmicrosoft.com; s=selector1-spirent-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=DAZ6hLmDgSxbHfydX6T+4JUbMmgB2WavEYfIKwvjoGg=; b=6bymxLWIapmy7uxA4m7/hRaikSvDuwWJlueC5qUmORUvwS8HbwiCIA/jECHzbqxaFQ9/ZxjK4xNNcirO2zUgOKdDvrp54wQmwIsIlYMj4ZrbN/FwdDVfIEkJf4b88QmqN6tw+Ed7OQPZFwaRWYCjpbOJiLHOaJ/lsMC7WQf6JZM= Received: from BN7PR10MB2739.namprd10.prod.outlook.com (20.176.21.18) by BN7PR10MB2660.namprd10.prod.outlook.com (20.176.20.148) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1709.13; Fri, 15 Mar 2019 19:09:15 +0000 Received: from BN7PR10MB2739.namprd10.prod.outlook.com ([fe80::48e7:efdb:42f5:d296]) by BN7PR10MB2739.namprd10.prod.outlook.com ([fe80::48e7:efdb:42f5:d296%3]) with mapi id 15.20.1686.021; Fri, 15 Mar 2019 19:09:15 +0000 From: "Player, Timmons" To: "stable@dpdk.org" CC: "Player, Timmons" Thread-Topic: [PATCH] net/igb: fix LSC interrupt when using MSI-X Thread-Index: AQHU22KUjAilG9ZBz0Kg4UxDMgrw+A== Date: Fri, 15 Mar 2019 19:09:15 +0000 Message-ID: <20190315190854.4486-1-timmons.player@spirent.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [136.56.16.131] x-clientproxiedby: BN6PR02CA0027.namprd02.prod.outlook.com (2603:10b6:404:5f::13) To BN7PR10MB2739.namprd10.prod.outlook.com (2603:10b6:406:c6::18) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Timmons.Player@spirent.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 38a7f569-1cad-409c-fb84-08d6a979b6e0 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(2017052603328)(7153060)(7193020); SRVR:BN7PR10MB2660; x-ms-traffictypediagnostic: BN7PR10MB2660: x-microsoft-antispam-prvs: x-forefront-prvs: 09778E995A x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(376002)(366004)(136003)(346002)(396003)(39850400004)(189003)(199004)(2616005)(476003)(486006)(86362001)(7736002)(97736004)(26005)(8936002)(106356001)(305945005)(5660300002)(1076003)(2351001)(72206003)(36756003)(1730700003)(81156014)(81166006)(186003)(52116002)(8676002)(50226002)(71190400001)(99286004)(2501003)(71200400001)(68736007)(6486002)(6506007)(25786009)(14454004)(102836004)(6916009)(386003)(4326008)(53936002)(66066001)(6436002)(316002)(107886003)(105586002)(5640700003)(6512007)(256004)(14444005)(478600001)(6116002)(2906002)(3846002); DIR:OUT; SFP:1102; SCL:1; SRVR:BN7PR10MB2660; H:BN7PR10MB2739.namprd10.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: spirent.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 3cox0zwvO6jUMe1IVUYOyJnrWzPH/i9BjUnhnXhv1cCpMKVtjffyH1VgRR3FoCreWRznGQzI/P6vrkWOWDF8Y5j90BA2cieITYbp+dJI3mn5P+Ic/QvVB2bMER+0bI8ZHxY29T0a46WeF3scDPtlzMaLiJvwvkZgK8LkLObUaq8t8hzig5OcHd3hJes6RWlJVILvneUFzKF+egAoJs+JEcPK6C96F0NDJJTY5KDh+UilkWy5CkRVuot4VG0FVmOBacey26sfFNH4NYjjr1qvF1yIULf00PFuG2Y+ztrsw97wjmBK+tvnzAeYCLhdNxCrTzovqidzNb6lYB7+N6BuJh03UyZQcR+LBoQkz6qDk9H4x7ytJUbt0vfSCiQ6ZyEkNaL1aJgZkyDmTcC9/D0Neq8XiAt4H/nWjUEfNZZHzJU= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: spirent.com X-MS-Exchange-CrossTenant-Network-Message-Id: 38a7f569-1cad-409c-fb84-08d6a979b6e0 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2019 19:09:15.3945 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: eb68cad0-6bd5-483f-a802-0f72f974373f X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR10MB2660 Subject: [dpdk-stable] [PATCH] net/igb: fix LSC interrupt when using MSI-X X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" [ backported from upstream commit 7f5c81d5689d4d1b4dce8279a6eb3318bddf1607 = ] Take the 'other interrupt' into account when setting up MSI-X interrupts and use the proper mask when enabling it. Also, rearm the MSI-X vector after the LSC interrupt fires. This change allows both LSC and RXQ interrupts to work at the same time when using MSI-X interrupts. Signed-off-by: Timmons C. Player --- drivers/net/e1000/igb_ethdev.c | 43 +++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.= c index fdc139f35..6410608d9 100644 --- a/drivers/net/e1000/igb_ethdev.c +++ b/drivers/net/e1000/igb_ethdev.c @@ -100,6 +100,9 @@ #define E1000_VET_VET_EXT 0xFFFF0000 #define E1000_VET_VET_EXT_SHIFT 16 =20 +/* MSI-X other interrupt vector */ +#define IGB_MSIX_OTHER_INTR_VEC 0 + static int eth_igb_configure(struct rte_eth_dev *dev); static int eth_igb_start(struct rte_eth_dev *dev); static void eth_igb_stop(struct rte_eth_dev *dev); @@ -169,7 +172,7 @@ static void igb_vlan_hw_extend_disable(struct rte_eth_d= ev *dev); static int eth_igb_led_on(struct rte_eth_dev *dev); static int eth_igb_led_off(struct rte_eth_dev *dev); =20 -static void igb_intr_disable(struct e1000_hw *hw); +static void igb_intr_disable(struct rte_eth_dev *dev); static int igb_get_rx_buffer_size(struct e1000_hw *hw); static int eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr, @@ -610,14 +613,31 @@ igb_intr_enable(struct rte_eth_dev *dev) E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); struct e1000_hw *hw =3D E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; + + if (rte_intr_allow_others(intr_handle) && + dev->data->dev_conf.intr_conf.lsc !=3D 0) { + E1000_WRITE_REG(hw, E1000_EIMS, 1 << IGB_MSIX_OTHER_INTR_VEC); + } =20 E1000_WRITE_REG(hw, E1000_IMS, intr->mask); E1000_WRITE_FLUSH(hw); } =20 static void -igb_intr_disable(struct e1000_hw *hw) +igb_intr_disable(struct rte_eth_dev *dev) { + struct e1000_hw *hw =3D + E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; + + if (rte_intr_allow_others(intr_handle) && + dev->data->dev_conf.intr_conf.lsc !=3D 0) { + E1000_WRITE_REG(hw, E1000_EIMC, 1 << IGB_MSIX_OTHER_INTR_VEC); + } + E1000_WRITE_REG(hw, E1000_IMC, ~0); E1000_WRITE_FLUSH(hw); } @@ -1529,7 +1549,7 @@ eth_igb_stop(struct rte_eth_dev *dev) struct rte_eth_link link; struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; =20 - igb_intr_disable(hw); + igb_intr_disable(dev); =20 /* disable intr eventfd mapping */ rte_intr_disable(intr_handle); @@ -2792,12 +2812,15 @@ static int eth_igb_rxq_interrupt_setup(struct rte_e= th_dev *dev) uint32_t mask, regval; struct e1000_hw *hw =3D E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_pci_device *pci_dev =3D RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle =3D &pci_dev->intr_handle; + int misc_shift =3D rte_intr_allow_others(intr_handle) ? 1 : 0; struct rte_eth_dev_info dev_info; =20 memset(&dev_info, 0, sizeof(dev_info)); eth_igb_infos_get(dev, &dev_info); =20 - mask =3D 0xFFFFFFFF >> (32 - dev_info.max_rx_queues); + mask =3D (0xFFFFFFFF >> (32 - dev_info.max_rx_queues)) << misc_shift; regval =3D E1000_READ_REG(hw, E1000_EIMS); E1000_WRITE_REG(hw, E1000_EIMS, regval | mask); =20 @@ -2824,7 +2847,7 @@ eth_igb_interrupt_get_status(struct rte_eth_dev *dev) struct e1000_interrupt *intr =3D E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private); =20 - igb_intr_disable(hw); + igb_intr_disable(dev); =20 /* read-on-clear nic registers here */ icr =3D E1000_READ_REG(hw, E1000_ICR); @@ -5534,13 +5557,17 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev= ) E1000_GPIE_NSICR); intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift; + + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); + regval =3D E1000_READ_REG(hw, E1000_EIAC); E1000_WRITE_REG(hw, E1000_EIAC, regval | intr_mask); =20 /* enable msix_other interrupt */ regval =3D E1000_READ_REG(hw, E1000_EIMS); E1000_WRITE_REG(hw, E1000_EIMS, regval | intr_mask); - tmpval =3D (dev->data->nb_rx_queues | E1000_IVAR_VALID) << 8; + tmpval =3D (IGB_MSIX_OTHER_INTR_VEC | E1000_IVAR_VALID) << 8; E1000_WRITE_REG(hw, E1000_IVAR_MISC, tmpval); } =20 @@ -5549,6 +5576,10 @@ eth_igb_configure_msix_intr(struct rte_eth_dev *dev) */ intr_mask =3D RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift; + + if (dev->data->dev_conf.intr_conf.lsc !=3D 0) + intr_mask |=3D (1 << IGB_MSIX_OTHER_INTR_VEC); + regval =3D E1000_READ_REG(hw, E1000_EIAM); E1000_WRITE_REG(hw, E1000_EIAM, regval | intr_mask); =20 --=20 2.17.1