From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 6327EA0679 for ; Tue, 30 Apr 2019 22:28:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A88C5293B; Tue, 30 Apr 2019 22:28:24 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 98029293B for ; Tue, 30 Apr 2019 22:28:22 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE2 (envelope-from yskoh@mellanox.com) with ESMTPS (AES256-SHA encrypted); 30 Apr 2019 23:28:20 +0300 Received: from scfae-sc-2.mti.labs.mlnx (scfae-sc-2.mti.labs.mlnx [10.101.0.96]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x3UKSIVU025068; Tue, 30 Apr 2019 23:28:18 +0300 From: Yongseok Koh To: yskoh@mellanox.com Cc: stable@dpdk.org, shahafs@mellanox.com Date: Tue, 30 Apr 2019 13:28:12 -0700 Message-Id: <20190430202812.36457-1-yskoh@mellanox.com> X-Mailer: git-send-email 2.11.0 Subject: [dpdk-stable] [PATCH 17.11] net/mlx5: fix instruction hotspot on replenishing Rx buffer X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" On replenishing Rx buffers for vectorized Rx, mbuf->buf_addr isn't needed to be accessed as it is static and easily calculated from the mbuf address. Accessing the mbuf content causes unnecessary load stall. non-x86 processors (mostly RISC such as ARM and Power) are more vulnerable to load stall. For x86, reducing the number of instructions seems to matter most. Fixes: 545b884b1da3 ("net/mlx5: fix buffer address posting in SSE Rx") Signed-off-by: Yongseok Koh Acked-by: Shahaf Shuler --- drivers/net/mlx5/mlx5_rxtx_vec.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.h b/drivers/net/mlx5/mlx5_rxtx_vec.h index 750559b8d..e7367b74d 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec.h @@ -116,7 +116,22 @@ mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n) return; } for (i = 0; i < n; ++i) { - wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr + + void *buf_addr; + + /* + * Load the virtual address for Rx WQE. non-x86 processors + * (mostly RISC such as ARM and Power) are more vulnerable to + * load stall. For x86, reducing the number of instructions + * seems to matter most. + */ +#ifdef RTE_ARCH_X86_64 + buf_addr = elts[i]->buf_addr; +#else + buf_addr = (char *)elts[i] + sizeof(struct rte_mbuf) + + rte_pktmbuf_priv_size(rxq->mp); + assert(buf_addr == elts[i]->buf_addr); +#endif + wq[i].addr = rte_cpu_to_be_64((uintptr_t)buf_addr + RTE_PKTMBUF_HEADROOM); /* If there's only one MR, no need to replace LKEY in WQEs. */ if (unlikely(!IS_SINGLE_MR(rxq->mr_ctrl.bh_n))) -- 2.11.0