From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8F2C6A04C3 for ; Fri, 22 Nov 2019 15:43:03 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 826AE91; Fri, 22 Nov 2019 15:43:03 +0100 (CET) Received: from us-smtp-delivery-1.mimecast.com (us-smtp-2.mimecast.com [207.211.31.81]) by dpdk.org (Postfix) with ESMTP id 52FC5235 for ; Fri, 22 Nov 2019 15:43:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1574433781; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UJcQbgaqcdoVlbbYBzaAxl9Cc+u0EApmcMSknJzUPHw=; b=QpY1jEg5lvhIg2f1ZG0mCqxcw0qFaYPau/ZY6peI75xUKOLq8JHsu6tHXBS0NmuzzoNxH+ 637+W7CncczDWafXnyUY1wvFI5+6Ho84fL/vu0bSnyvnRMP97ecmvfdblUaxpmEQPg2UKg TUoCORwgY03TIKTRaQoyhfCLg2yCtZw= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-245-cK2k0vCENsisIqGehzWG7w-1; Fri, 22 Nov 2019 09:43:00 -0500 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 18230107ACC5; Fri, 22 Nov 2019 14:42:59 +0000 (UTC) Received: from rh.redhat.com (unknown [10.36.118.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id C92D58516; Fri, 22 Nov 2019 14:42:57 +0000 (UTC) From: Kevin Traynor To: Shahed Shaikh Cc: dpdk stable Date: Fri, 22 Nov 2019 14:41:26 +0000 Message-Id: <20191122144131.21231-40-ktraynor@redhat.com> In-Reply-To: <20191122144131.21231-1-ktraynor@redhat.com> References: <20191122144131.21231-1-ktraynor@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-MC-Unique: cK2k0vCENsisIqGehzWG7w-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Subject: [dpdk-stable] patch 'net/qede: fix odd number of queues usage in 100G mode' has been queued to LTS release 18.11.6 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to LTS release 18.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/29/19. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasi= ng (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/kevintraynor/dpdk-stable-queue This queued commit can be viewed at: https://github.com/kevintraynor/dpdk-stable-queue/commit/eabce98f4b64f75aad= c746760e221ad7b8bd4012 Thanks. Kevin. --- >From eabce98f4b64f75aadc746760e221ad7b8bd4012 Mon Sep 17 00:00:00 2001 From: Shahed Shaikh Date: Thu, 12 Sep 2019 08:24:13 -0700 Subject: [PATCH] net/qede: fix odd number of queues usage in 100G mode [ upstream commit 8de0c42019260813b71699748a08bc94b608b5d9 ] As per HW design of 100Gb mode, device internally uses 2 engines (eng0 and eng1), and both engines need to be configured symmetrically. Based on this requirement, driver design chose an approach to allow user to allocate only even number of queues and split those queues on both engines equally. This approach puts a limitation on number of queues to be allocated - i.e. user can't configure odd number of queues on 100Gb mode. OVS configures DPDK port with 1 rxq and 1 txq, which causes initialization of qede port to fail. Issue is fixed by changing the implementation of queue allocation and assignment to hw engines only for 100Gb devices and allowing user to configure odd number queues. New approach works as below - - Create 'struct qede_fastpath_cmt' to hold hw queue pair of both engines and provide it to rte_ethdev's Rx/Tx queues structure. - So ethdev will see only one queue for underlying queue pair created for hw engine pair. - Install separate Rx/Tx data path handlers for 100Gb mode and regular mode - Rx/Tx handlers for 100Gb mode will split packet processing across both engines by providing hw queue structures from 'struct qede_fastpath_cmt' passed by Rx/Tx callbacks to respective engines. Fixes: 2af14ca79c0a ("net/qede: support 100G") Signed-off-by: Shahed Shaikh --- drivers/net/qede/qede_ethdev.c | 112 ++++++++++++----------- drivers/net/qede/qede_ethdev.h | 5 +- drivers/net/qede/qede_filter.c | 5 +- drivers/net/qede/qede_rxtx.c | 161 +++++++++++++++++++++++++++------ drivers/net/qede/qede_rxtx.h | 26 +++++- 5 files changed, 219 insertions(+), 90 deletions(-) diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.= c index c4f5ad1ed..de8e26f51 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -304,4 +304,5 @@ static void qede_print_adapter_info(struct qede_dev *qd= ev) static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats) { +=09struct rte_eth_dev *dev =3D (struct rte_eth_dev *)qdev->ethdev; =09struct ecore_dev *edev =3D QEDE_INIT_EDEV(qdev); =09unsigned int i =3D 0, j =3D 0, qid; @@ -311,10 +312,10 @@ static void qede_reset_queue_stats(struct qede_dev *q= dev, bool xstats) =09DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n"); =20 -=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(qdev), +=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(dev), =09=09=09 RTE_ETHDEV_QUEUE_STAT_CNTRS); -=09txq_stat_cntrs =3D RTE_MIN(QEDE_TSS_COUNT(qdev), +=09txq_stat_cntrs =3D RTE_MIN(QEDE_TSS_COUNT(dev), =09=09=09 RTE_ETHDEV_QUEUE_STAT_CNTRS); =20 -=09for_each_rss(qid) { +=09for (qid =3D 0; qid < qdev->num_rx_queues; qid++) { =09=09OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) + =09=09=09 offsetof(struct qede_rx_queue, rcv_pkts), 0, @@ -342,5 +343,5 @@ static void qede_reset_queue_stats(struct qede_dev *qde= v, bool xstats) =09i =3D 0; =20 -=09for_each_tss(qid) { +=09for (qid =3D 0; qid < qdev->num_tx_queues; qid++) { =09=09txq =3D qdev->fp_array[qid].txq; =20 @@ -989,5 +990,5 @@ int qede_config_rss(struct rte_eth_dev *eth_dev) =09=09id =3D i / RTE_RETA_GROUP_SIZE; =09=09pos =3D i % RTE_RETA_GROUP_SIZE; -=09=09q =3D i % QEDE_RSS_COUNT(qdev); +=09=09q =3D i % QEDE_RSS_COUNT(eth_dev); =09=09reta_conf[id].reta[pos] =3D q; =09} @@ -1163,20 +1164,4 @@ static int qede_dev_configure(struct rte_eth_dev *et= h_dev) =09PMD_INIT_FUNC_TRACE(edev); =20 -=09/* Check requirements for 100G mode */ -=09if (ECORE_IS_CMT(edev)) { -=09=09if (eth_dev->data->nb_rx_queues < 2 || -=09=09 eth_dev->data->nb_tx_queues < 2) { -=09=09=09DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n"); -=09=09=09return -EINVAL; -=09=09} - -=09=09if ((eth_dev->data->nb_rx_queues % 2 !=3D 0) || -=09=09 (eth_dev->data->nb_tx_queues % 2 !=3D 0)) { -=09=09=09DP_ERR(edev, -=09=09=09 "100G mode needs even no. of RX/TX queues\n"); -=09=09=09return -EINVAL; -=09=09} -=09} - =09/* We need to have min 1 RX queue.There is no min check in =09 * rte_eth_dev_configure(), so we are checking it here. @@ -1205,6 +1190,7 @@ static int qede_dev_configure(struct rte_eth_dev *eth= _dev) =20 =09qede_dealloc_fp_resc(eth_dev); -=09qdev->num_tx_queues =3D eth_dev->data->nb_tx_queues; -=09qdev->num_rx_queues =3D eth_dev->data->nb_rx_queues; +=09qdev->num_tx_queues =3D eth_dev->data->nb_tx_queues * edev->num_hwfns; +=09qdev->num_rx_queues =3D eth_dev->data->nb_rx_queues * edev->num_hwfns; + =09if (qede_alloc_fp_resc(qdev)) =09=09return -ENOMEM; @@ -1231,5 +1217,10 @@ static int qede_dev_configure(struct rte_eth_dev *et= h_dev) =20 =09DP_INFO(edev, "Device configured with RSS=3D%d TSS=3D%d\n", -=09=09=09QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev)); +=09=09=09QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev)); + +=09if (ECORE_IS_CMT(edev)) +=09=09DP_INFO(edev, "Actual HW queues for CMT mode - RX =3D %d TX =3D %d\n= ", +=09=09=09qdev->num_rx_queues, qdev->num_tx_queues); + =20 =09return 0; @@ -1273,4 +1264,8 @@ qede_dev_info_get(struct rte_eth_dev *eth_dev, =09=09dev_info->max_rx_queues =3D (uint16_t)RTE_MIN( =09=09=09QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF); +=09/* Since CMT mode internally doubles the number of queues */ +=09if (ECORE_IS_CMT(edev)) +=09=09dev_info->max_rx_queues =3D dev_info->max_rx_queues / 2; + =09dev_info->max_tx_queues =3D dev_info->max_rx_queues; =20 @@ -1516,10 +1511,10 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct = rte_eth_stats *eth_stats) =20 =09/* Queue stats */ -=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(qdev), +=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(eth_dev), =09=09=09 RTE_ETHDEV_QUEUE_STAT_CNTRS); -=09txq_stat_cntrs =3D RTE_MIN(QEDE_TSS_COUNT(qdev), +=09txq_stat_cntrs =3D RTE_MIN(QEDE_TSS_COUNT(eth_dev), =09=09=09 RTE_ETHDEV_QUEUE_STAT_CNTRS); -=09if ((rxq_stat_cntrs !=3D (unsigned int)QEDE_RSS_COUNT(qdev)) || -=09 (txq_stat_cntrs !=3D (unsigned int)QEDE_TSS_COUNT(qdev))) +=09if (rxq_stat_cntrs !=3D (unsigned int)QEDE_RSS_COUNT(eth_dev) || +=09 txq_stat_cntrs !=3D (unsigned int)QEDE_TSS_COUNT(eth_dev)) =09=09DP_VERBOSE(edev, ECORE_MSG_DEBUG, =09=09 "Not all the queue stats will be displayed. Set" @@ -1527,5 +1522,5 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct rt= e_eth_stats *eth_stats) =09=09 " appropriately and retry.\n"); =20 -=09for_each_rss(qid) { +=09for (qid =3D 0; qid < eth_dev->data->nb_rx_queues; qid++) { =09=09eth_stats->q_ipackets[i] =3D =09=09=09*(uint64_t *)( @@ -1547,5 +1542,5 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct rt= e_eth_stats *eth_stats) =09} =20 -=09for_each_tss(qid) { +=09for (qid =3D 0; qid < eth_dev->data->nb_tx_queues; qid++) { =09=09txq =3D qdev->fp_array[qid].txq; =09=09eth_stats->q_opackets[j] =3D @@ -1564,16 +1559,16 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct = rte_eth_stats *eth_stats) static unsigned qede_get_xstats_count(struct qede_dev *qdev) { +=09struct rte_eth_dev *dev =3D (struct rte_eth_dev *)qdev->ethdev; + =09if (ECORE_IS_BB(&qdev->edev)) =09=09return RTE_DIM(qede_xstats_strings) + =09=09 RTE_DIM(qede_bb_xstats_strings) + =09=09 (RTE_DIM(qede_rxq_xstats_strings) * -=09=09=09RTE_MIN(QEDE_RSS_COUNT(qdev), -=09=09=09=09RTE_ETHDEV_QUEUE_STAT_CNTRS)); +=09=09=09QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns); =09else =09=09return RTE_DIM(qede_xstats_strings) + =09=09 RTE_DIM(qede_ah_xstats_strings) + =09=09 (RTE_DIM(qede_rxq_xstats_strings) * -=09=09=09RTE_MIN(QEDE_RSS_COUNT(qdev), -=09=09=09=09RTE_ETHDEV_QUEUE_STAT_CNTRS)); +=09=09=09QEDE_RSS_COUNT(dev)); } =20 @@ -1616,5 +1611,5 @@ qede_get_xstats_names(struct rte_eth_dev *dev, =09=09} =20 -=09=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(qdev), +=09=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(dev), =09=09=09=09=09 RTE_ETHDEV_QUEUE_STAT_CNTRS); =09=09for (qid =3D 0; qid < rxq_stat_cntrs; qid++) { @@ -1674,15 +1669,13 @@ qede_get_xstats(struct rte_eth_dev *dev, struct rte= _eth_xstat *xstats, =09} =20 -=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(qdev), +=09rxq_stat_cntrs =3D RTE_MIN(QEDE_RSS_COUNT(dev), =09=09=09=09 RTE_ETHDEV_QUEUE_STAT_CNTRS); =09for (qid =3D 0; qid < rxq_stat_cntrs; qid++) { -=09=09for_each_rss(qid) { -=09=09=09for (i =3D 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { -=09=09=09=09xstats[stat_idx].value =3D *(uint64_t *)( -=09=09=09=09=09((char *)(qdev->fp_array[qid].rxq)) + -=09=09=09=09=09 qede_rxq_xstats_strings[i].offset); -=09=09=09=09xstats[stat_idx].id =3D stat_idx; -=09=09=09=09stat_idx++; -=09=09=09} +=09=09for (i =3D 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) { +=09=09=09xstats[stat_idx].value =3D *(uint64_t *) +=09=09=09=09(((char *)(qdev->fp_array[qid].rxq)) + +=09=09=09=09 qede_rxq_xstats_strings[i].offset); +=09=09=09xstats[stat_idx].id =3D stat_idx; +=09=09=09stat_idx++; =09=09} =09} @@ -1938,5 +1931,6 @@ qede_dev_supported_ptypes_get(struct rte_eth_dev *eth= _dev) =09}; =20 -=09if (eth_dev->rx_pkt_burst =3D=3D qede_recv_pkts) +=09if (eth_dev->rx_pkt_burst =3D=3D qede_recv_pkts || +=09 eth_dev->rx_pkt_burst =3D=3D qede_recv_pkts_cmt) =09=09return ptypes; =20 @@ -2005,5 +1999,5 @@ int qede_rss_hash_update(struct rte_eth_dev *eth_dev, =09/* pass the L2 handles instead of qids */ =09for (i =3D 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) { -=09=09idx =3D i % QEDE_RSS_COUNT(qdev); +=09=09idx =3D i % QEDE_RSS_COUNT(eth_dev); =09=09rss_params.rss_ind_table[i] =3D qdev->fp_array[idx].rxq->handle; =09} @@ -2257,5 +2251,5 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uint= 16_t mtu) =20 =09/* Fix up RX buf size for all queues of the port */ -=09for_each_rss(i) { +=09for (i =3D 0; i < qdev->num_rx_queues; i++) { =09=09fp =3D &qdev->fp_array[i]; =09=09if (fp->rxq !=3D NULL) { @@ -2286,7 +2280,11 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uin= t16_t mtu) =09dev->data->dev_conf.rxmode.max_rx_pkt_len =3D max_rx_pkt_len; =09/* Reassign back */ -=09dev->rx_pkt_burst =3D qede_recv_pkts; -=09dev->tx_pkt_burst =3D qede_xmit_pkts; - +=09if (ECORE_IS_CMT(edev)) { +=09=09dev->rx_pkt_burst =3D qede_recv_pkts_cmt; +=09=09dev->tx_pkt_burst =3D qede_xmit_pkts_cmt; +=09} else { +=09=09dev->rx_pkt_burst =3D qede_recv_pkts; +=09=09dev->tx_pkt_burst =3D qede_xmit_pkts; +=09} =09return 0; } @@ -2429,8 +2427,4 @@ static int qede_common_dev_init(struct rte_eth_dev *e= th_dev, bool is_vf) =09=09 eth_dev->data->port_id); =20 -=09eth_dev->rx_pkt_burst =3D qede_recv_pkts; -=09eth_dev->tx_pkt_burst =3D qede_xmit_pkts; -=09eth_dev->tx_pkt_prepare =3D qede_xmit_prep_pkts; - =09if (rte_eal_process_type() !=3D RTE_PROC_PRIMARY) { =09=09DP_ERR(edev, "Skipping device init from secondary process\n"); @@ -2490,4 +2484,14 @@ static int qede_common_dev_init(struct rte_eth_dev *= eth_dev, bool is_vf) =09=09QEDE_PMD_DRV_VER_STR_SIZE); =20 +=09if (ECORE_IS_CMT(edev)) { +=09=09eth_dev->rx_pkt_burst =3D qede_recv_pkts_cmt; +=09=09eth_dev->tx_pkt_burst =3D qede_xmit_pkts_cmt; +=09} else { +=09=09eth_dev->rx_pkt_burst =3D qede_recv_pkts; +=09=09eth_dev->tx_pkt_burst =3D qede_xmit_pkts; +=09} + +=09eth_dev->tx_pkt_prepare =3D qede_xmit_prep_pkts; + =09/* For CMT mode device do periodic polling for slowpath events. =09 * This is required since uio device uses only one MSI-x diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.= h index c06274d94..735dfdb66 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -67,6 +67,6 @@ =20 #define QEDE_QUEUE_CNT(qdev) ((qdev)->num_queues) -#define QEDE_RSS_COUNT(qdev) ((qdev)->num_rx_queues) -#define QEDE_TSS_COUNT(qdev) ((qdev)->num_tx_queues) +#define QEDE_RSS_COUNT(dev) ((dev)->data->nb_rx_queues) +#define QEDE_TSS_COUNT(dev) ((dev)->data->nb_tx_queues) =20 #define QEDE_DUPLEX_FULL=091 @@ -216,4 +216,5 @@ struct qede_dev { =09struct ecore_sb_info *sb_array; =09struct qede_fastpath *fp_array; +=09struct qede_fastpath_cmt *fp_array_cmt; =09uint16_t mtu; =09bool enable_tx_switching; diff --git a/drivers/net/qede/qede_filter.c b/drivers/net/qede/qede_filter.= c index 0beade6d5..56ec91272 100644 --- a/drivers/net/qede/qede_filter.c +++ b/drivers/net/qede/qede_filter.c @@ -432,5 +432,5 @@ qede_fdir_filter_add(struct rte_eth_dev *eth_dev, =09} =20 -=09if (fdir->action.rx_queue >=3D QEDE_RSS_COUNT(qdev)) { +=09if (fdir->action.rx_queue >=3D QEDE_RSS_COUNT(eth_dev)) { =09=09DP_ERR(edev, "invalid queue number %u\n", =09=09 fdir->action.rx_queue); @@ -1344,5 +1344,4 @@ qede_flow_parse_actions(struct rte_eth_dev *dev, =09=09=09struct rte_flow *flow) { -=09struct qede_dev *qdev =3D QEDE_INIT_QDEV(dev); =09const struct rte_flow_action_queue *queue; =20 @@ -1359,5 +1358,5 @@ qede_flow_parse_actions(struct rte_eth_dev *dev, =09=09=09queue =3D actions->conf; =20 -=09=09=09if (queue->index >=3D QEDE_RSS_COUNT(qdev)) { +=09=09=09if (queue->index >=3D QEDE_RSS_COUNT(dev)) { =09=09=09=09rte_flow_error_set(error, EINVAL, =09=09=09=09=09=09 RTE_FLOW_ERROR_TYPE_ACTION, diff --git a/drivers/net/qede/qede_rxtx.c b/drivers/net/qede/qede_rxtx.c index 64fd9e063..ca1305f1b 100644 --- a/drivers/net/qede/qede_rxtx.c +++ b/drivers/net/qede/qede_rxtx.c @@ -261,11 +261,28 @@ qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t= qid, =09bufsz =3D rc; =20 -=09rxq =3D qede_alloc_rx_queue_mem(dev, qid, nb_desc, -=09=09=09=09 socket_id, mp, bufsz); -=09if (!rxq) -=09=09return -ENOMEM; +=09if (ECORE_IS_CMT(edev)) { +=09=09rxq =3D qede_alloc_rx_queue_mem(dev, qid * 2, nb_desc, +=09=09=09=09=09 socket_id, mp, bufsz); +=09=09if (!rxq) +=09=09=09return -ENOMEM; =20 -=09dev->data->rx_queues[qid] =3D rxq; -=09qdev->fp_array[qid].rxq =3D rxq; +=09=09qdev->fp_array[qid * 2].rxq =3D rxq; +=09=09rxq =3D qede_alloc_rx_queue_mem(dev, qid * 2 + 1, nb_desc, +=09=09=09=09=09 socket_id, mp, bufsz); +=09=09if (!rxq) +=09=09=09return -ENOMEM; + +=09=09qdev->fp_array[qid * 2 + 1].rxq =3D rxq; +=09=09/* provide per engine fp struct as rx queue */ +=09=09dev->data->rx_queues[qid] =3D &qdev->fp_array_cmt[qid]; +=09} else { +=09=09rxq =3D qede_alloc_rx_queue_mem(dev, qid, nb_desc, +=09=09=09=09=09 socket_id, mp, bufsz); +=09=09if (!rxq) +=09=09=09return -ENOMEM; + +=09=09dev->data->rx_queues[qid] =3D rxq; +=09=09qdev->fp_array[qid].rxq =3D rxq; +=09} =20 =09DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=3D%u socket %u\n", @@ -315,4 +332,5 @@ void qede_rx_queue_release(void *rx_queue) { =09struct qede_rx_queue *rxq =3D rx_queue; +=09struct qede_fastpath_cmt *fp_cmt; =09struct qede_dev *qdev; =09struct ecore_dev *edev; @@ -322,5 +340,11 @@ void qede_rx_queue_release(void *rx_queue) =09=09edev =3D QEDE_INIT_EDEV(qdev); =09=09PMD_INIT_FUNC_TRACE(edev); -=09=09_qede_rx_queue_release(qdev, edev, rxq); +=09=09if (ECORE_IS_CMT(edev)) { +=09=09=09fp_cmt =3D rx_queue; +=09=09=09_qede_rx_queue_release(qdev, edev, fp_cmt->fp0->rxq); +=09=09=09_qede_rx_queue_release(qdev, edev, fp_cmt->fp1->rxq); +=09=09} else { +=09=09=09_qede_rx_queue_release(qdev, edev, rxq); +=09=09} =09} } @@ -455,11 +479,28 @@ qede_tx_queue_setup(struct rte_eth_dev *dev, =09} =20 -=09txq =3D qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc, -=09=09=09=09 socket_id, tx_conf); -=09if (!txq) -=09=09return -ENOMEM; +=09if (ECORE_IS_CMT(edev)) { +=09=09txq =3D qede_alloc_tx_queue_mem(dev, queue_idx * 2, nb_desc, +=09=09=09=09=09 socket_id, tx_conf); +=09=09if (!txq) +=09=09=09return -ENOMEM; =20 -=09dev->data->tx_queues[queue_idx] =3D txq; -=09qdev->fp_array[queue_idx].txq =3D txq; +=09=09qdev->fp_array[queue_idx * 2].txq =3D txq; +=09=09txq =3D qede_alloc_tx_queue_mem(dev, (queue_idx * 2) + 1, nb_desc, +=09=09=09=09=09 socket_id, tx_conf); +=09=09if (!txq) +=09=09=09return -ENOMEM; + +=09=09qdev->fp_array[(queue_idx * 2) + 1].txq =3D txq; +=09=09dev->data->tx_queues[queue_idx] =3D +=09=09=09=09=09&qdev->fp_array_cmt[queue_idx]; +=09} else { +=09=09txq =3D qede_alloc_tx_queue_mem(dev, queue_idx, nb_desc, +=09=09=09=09=09 socket_id, tx_conf); +=09=09if (!txq) +=09=09=09return -ENOMEM; + +=09=09dev->data->tx_queues[queue_idx] =3D txq; +=09=09qdev->fp_array[queue_idx].txq =3D txq; +=09} =20 =09return 0; @@ -504,4 +545,5 @@ void qede_tx_queue_release(void *tx_queue) { =09struct qede_tx_queue *txq =3D tx_queue; +=09struct qede_fastpath_cmt *fp_cmt; =09struct qede_dev *qdev; =09struct ecore_dev *edev; @@ -511,5 +553,12 @@ void qede_tx_queue_release(void *tx_queue) =09=09edev =3D QEDE_INIT_EDEV(qdev); =09=09PMD_INIT_FUNC_TRACE(edev); -=09=09_qede_tx_queue_release(qdev, edev, txq); + +=09=09if (ECORE_IS_CMT(edev)) { +=09=09=09fp_cmt =3D tx_queue; +=09=09=09_qede_tx_queue_release(qdev, edev, fp_cmt->fp0->txq); +=09=09=09_qede_tx_queue_release(qdev, edev, fp_cmt->fp1->txq); +=09=09} else { +=09=09=09_qede_tx_queue_release(qdev, edev, txq); +=09=09} =09} } @@ -549,4 +598,5 @@ int qede_alloc_fp_resc(struct qede_dev *qdev) =09uint32_t num_sbs; =09uint16_t sb_idx; +=09int i; =20 =09if (IS_VF(edev)) @@ -572,4 +622,26 @@ int qede_alloc_fp_resc(struct qede_dev *qdev) =09=09=09sizeof(*qdev->fp_array)); =20 +=09if (ECORE_IS_CMT(edev)) { +=09=09qdev->fp_array_cmt =3D rte_calloc("fp_cmt", +=09=09=09=09=09=09QEDE_RXTX_MAX(qdev) / 2, +=09=09=09=09=09=09sizeof(*qdev->fp_array_cmt), +=09=09=09=09=09=09RTE_CACHE_LINE_SIZE); + +=09=09if (!qdev->fp_array_cmt) { +=09=09=09DP_ERR(edev, "fp array for CMT allocation failed\n"); +=09=09=09return -ENOMEM; +=09=09} + +=09=09memset((void *)qdev->fp_array_cmt, 0, +=09=09 (QEDE_RXTX_MAX(qdev) / 2) * sizeof(*qdev->fp_array_cmt)); + +=09=09/* Establish the mapping of fp_array with fp_array_cmt */ +=09=09for (i =3D 0; i < QEDE_RXTX_MAX(qdev) / 2; i++) { +=09=09=09qdev->fp_array_cmt[i].qdev =3D qdev; +=09=09=09qdev->fp_array_cmt[i].fp0 =3D &qdev->fp_array[i * 2]; +=09=09=09qdev->fp_array_cmt[i].fp1 =3D &qdev->fp_array[i * 2 + 1]; +=09=09} +=09} + =09for (sb_idx =3D 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) { =09=09fp =3D &qdev->fp_array[sb_idx]; @@ -636,4 +708,8 @@ void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev) =09=09rte_free(qdev->fp_array); =09qdev->fp_array =3D NULL; + +=09if (qdev->fp_array_cmt) +=09=09rte_free(qdev->fp_array_cmt); +=09qdev->fp_array_cmt =3D NULL; } =20 @@ -687,7 +763,7 @@ qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16= _t rx_queue_id) =09int rc; =20 -=09if (rx_queue_id < eth_dev->data->nb_rx_queues) { +=09if (rx_queue_id < qdev->num_rx_queues) { =09=09fp =3D &qdev->fp_array[rx_queue_id]; -=09=09rxq =3D eth_dev->data->rx_queues[rx_queue_id]; +=09=09rxq =3D fp->rxq; =09=09/* Allocate buffers for the Rx ring */ =09=09for (j =3D 0; j < rxq->nb_rx_desc; j++) { @@ -758,7 +834,7 @@ qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16= _t tx_queue_id) =09int rc; =20 -=09if (tx_queue_id < eth_dev->data->nb_tx_queues) { -=09=09txq =3D eth_dev->data->tx_queues[tx_queue_id]; +=09if (tx_queue_id < qdev->num_tx_queues) { =09=09fp =3D &qdev->fp_array[tx_queue_id]; +=09=09txq =3D fp->txq; =09=09memset(¶ms, 0, sizeof(params)); =09=09params.queue_id =3D tx_queue_id / edev->num_hwfns; @@ -901,6 +977,6 @@ static int qede_tx_queue_stop(struct rte_eth_dev *eth_d= ev, uint16_t tx_queue_id) =09int rc; =20 -=09if (tx_queue_id < eth_dev->data->nb_tx_queues) { -=09=09txq =3D eth_dev->data->tx_queues[tx_queue_id]; +=09if (tx_queue_id < qdev->num_tx_queues) { +=09=09txq =3D qdev->fp_array[tx_queue_id].txq; =09=09/* Drain txq */ =09=09if (qede_drain_txq(qdev, txq, true)) @@ -933,5 +1009,5 @@ int qede_start_queues(struct rte_eth_dev *eth_dev) =09int rc =3D -1; =20 -=09for_each_rss(id) { +=09for (id =3D 0; id < qdev->num_rx_queues; id++) { =09=09rc =3D qede_rx_queue_start(eth_dev, id); =09=09if (rc !=3D ECORE_SUCCESS) @@ -939,5 +1015,5 @@ int qede_start_queues(struct rte_eth_dev *eth_dev) =09} =20 -=09for_each_tss(id) { +=09for (id =3D 0; id < qdev->num_tx_queues; id++) { =09=09rc =3D qede_tx_queue_start(eth_dev, id); =09=09if (rc !=3D ECORE_SUCCESS) @@ -954,11 +1030,9 @@ void qede_stop_queues(struct rte_eth_dev *eth_dev) =20 =09/* Stopping RX/TX queues */ -=09for_each_tss(id) { +=09for (id =3D 0; id < qdev->num_tx_queues; id++) =09=09qede_tx_queue_stop(eth_dev, id); -=09} =20 -=09for_each_rss(id) { +=09for (id =3D 0; id < qdev->num_rx_queues; id++) =09=09qede_rx_queue_stop(eth_dev, id); -=09} } =20 @@ -1740,4 +1814,21 @@ next_cqe: } =20 +uint16_t +qede_recv_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **rx_pkts, uint16_t nb_= pkts) +{ +=09struct qede_fastpath_cmt *fp_cmt =3D p_fp_cmt; +=09uint16_t eng0_pkts, eng1_pkts; + +=09eng0_pkts =3D nb_pkts / 2; + +=09eng0_pkts =3D qede_recv_pkts(fp_cmt->fp0->rxq, rx_pkts, eng0_pkts); + +=09eng1_pkts =3D nb_pkts - eng0_pkts; + +=09eng1_pkts =3D qede_recv_pkts(fp_cmt->fp1->rxq, rx_pkts + eng0_pkts, +=09=09=09=09 eng1_pkts); + +=09return eng0_pkts + eng1_pkts; +} =20 /* Populate scatter gather buffer descriptor fields */ @@ -2262,4 +2353,22 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkt= s, uint16_t nb_pkts) } =20 +uint16_t +qede_xmit_pkts_cmt(void *p_fp_cmt, struct rte_mbuf **tx_pkts, uint16_t nb_= pkts) +{ +=09struct qede_fastpath_cmt *fp_cmt =3D p_fp_cmt; +=09uint16_t eng0_pkts, eng1_pkts; + +=09eng0_pkts =3D nb_pkts / 2; + +=09eng0_pkts =3D qede_xmit_pkts(fp_cmt->fp0->txq, tx_pkts, eng0_pkts); + +=09eng1_pkts =3D nb_pkts - eng0_pkts; + +=09eng1_pkts =3D qede_xmit_pkts(fp_cmt->fp1->txq, tx_pkts + eng0_pkts, +=09=09=09=09 eng1_pkts); + +=09return eng0_pkts + eng1_pkts; +} + uint16_t qede_rxtx_pkts_dummy(__rte_unused void *p_rxq, diff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h index 5b249cbb2..4a1435663 100644 --- a/drivers/net/qede/qede_rxtx.h +++ b/drivers/net/qede/qede_rxtx.h @@ -82,8 +82,6 @@ =09=09=09=09 ETH_RSS_GENEVE) =20 -#define for_each_rss(i)=09=09for (i =3D 0; i < qdev->num_rx_queues; i++) -#define for_each_tss(i)=09=09for (i =3D 0; i < qdev->num_tx_queues; i++) #define QEDE_RXTX_MAX(qdev) \ -=09(RTE_MAX(QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev))) +=09(RTE_MAX(qdev->num_rx_queues, qdev->num_tx_queues)) =20 /* Macros for non-tunnel packet types lkup table */ @@ -180,4 +178,6 @@ struct qede_agg_info { */ struct qede_rx_queue { +=09/* Always keep qdev as first member */ +=09struct qede_dev *qdev; =09struct rte_mempool *mb_pool; =09struct ecore_chain rx_bd_ring; @@ -200,5 +200,4 @@ struct qede_rx_queue { =09uint64_t rx_alloc_errors; =09struct qede_agg_info tpa_info[ETH_TPA_MAX_AGGS_NUM]; -=09struct qede_dev *qdev; =09void *handle; }; @@ -218,4 +217,6 @@ union db_prod { =20 struct qede_tx_queue { +=09/* Always keep qdev as first member */ +=09struct qede_dev *qdev; =09struct ecore_chain tx_pbl; =09struct qede_tx_entry *sw_tx_ring; @@ -232,5 +233,4 @@ struct qede_tx_queue { =09uint64_t xmit_pkts; =09bool is_legacy; -=09struct qede_dev *qdev; =09void *handle; }; @@ -242,4 +242,16 @@ struct qede_fastpath { }; =20 +/* This structure holds the inforation of fast path queues + * belonging to individual engines in CMT mode. + */ +struct qede_fastpath_cmt { +=09/* Always keep this a first element */ +=09struct qede_dev *qdev; +=09/* fastpath info of engine 0 */ +=09struct qede_fastpath *fp0; +=09/* fastpath info of engine 1 */ +=09struct qede_fastpath *fp1; +}; + /* * RX/TX function prototypes @@ -262,4 +274,6 @@ void qede_tx_queue_release(void *tx_queue); uint16_t qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, =09=09=09uint16_t nb_pkts); +uint16_t qede_xmit_pkts_cmt(void *p_txq, struct rte_mbuf **tx_pkts, +=09=09=09 uint16_t nb_pkts); =20 uint16_t qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts, @@ -268,4 +282,6 @@ uint16_t qede_xmit_prep_pkts(void *p_txq, struct rte_mb= uf **tx_pkts, uint16_t qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, =09=09=09uint16_t nb_pkts); +uint16_t qede_recv_pkts_cmt(void *p_rxq, struct rte_mbuf **rx_pkts, +=09=09=09 uint16_t nb_pkts); =20 uint16_t qede_rxtx_pkts_dummy(void *p_rxq, --=20 2.21.0 --- Diff of the applied patch vs upstream commit (please double-check if non-= empty: --- --- -=092019-11-22 14:36:57.332808095 +0000 +++ 0040-net-qede-fix-odd-number-of-queues-usage-in-100G-mode.patch=092019-= 11-22 14:36:55.221148773 +0000 @@ -1 +1 @@ -From 8de0c42019260813b71699748a08bc94b608b5d9 Mon Sep 17 00:00:00 2001 +From eabce98f4b64f75aadc746760e221ad7b8bd4012 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 8de0c42019260813b71699748a08bc94b608b5d9 ] + @@ -32 +33,0 @@ -Cc: stable@dpdk.org @@ -44 +45 @@ -index 528b33e8c..308588cb8 100644 +index c4f5ad1ed..de8e26f51 100644 @@ -47 +48 @@ -@@ -305,4 +305,5 @@ static void qede_print_adapter_info(struct qede_dev *q= dev) +@@ -304,4 +304,5 @@ static void qede_print_adapter_info(struct qede_dev *q= dev) @@ -53 +54 @@ -@@ -312,10 +313,10 @@ static void qede_reset_queue_stats(struct qede_dev *= qdev, bool xstats) +@@ -311,10 +312,10 @@ static void qede_reset_queue_stats(struct qede_dev *= qdev, bool xstats) @@ -67 +68 @@ -@@ -343,5 +344,5 @@ static void qede_reset_queue_stats(struct qede_dev *qd= ev, bool xstats) +@@ -342,5 +343,5 @@ static void qede_reset_queue_stats(struct qede_dev *qd= ev, bool xstats) @@ -74 +75 @@ -@@ -992,5 +993,5 @@ int qede_config_rss(struct rte_eth_dev *eth_dev) +@@ -989,5 +990,5 @@ int qede_config_rss(struct rte_eth_dev *eth_dev) @@ -81 +82 @@ -@@ -1166,20 +1167,4 @@ static int qede_dev_configure(struct rte_eth_dev *e= th_dev) +@@ -1163,20 +1164,4 @@ static int qede_dev_configure(struct rte_eth_dev *e= th_dev) @@ -102 +103 @@ -@@ -1208,6 +1193,7 @@ static int qede_dev_configure(struct rte_eth_dev *et= h_dev) +@@ -1205,6 +1190,7 @@ static int qede_dev_configure(struct rte_eth_dev *et= h_dev) @@ -112 +113 @@ -@@ -1234,5 +1220,10 @@ static int qede_dev_configure(struct rte_eth_dev *e= th_dev) +@@ -1231,5 +1217,10 @@ static int qede_dev_configure(struct rte_eth_dev *e= th_dev) @@ -124 +125 @@ -@@ -1276,4 +1267,8 @@ qede_dev_info_get(struct rte_eth_dev *eth_dev, +@@ -1273,4 +1264,8 @@ qede_dev_info_get(struct rte_eth_dev *eth_dev, @@ -133 +134 @@ -@@ -1519,10 +1514,10 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct= rte_eth_stats *eth_stats) +@@ -1516,10 +1511,10 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct= rte_eth_stats *eth_stats) @@ -148 +149 @@ -@@ -1530,5 +1525,5 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct r= te_eth_stats *eth_stats) +@@ -1527,5 +1522,5 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct r= te_eth_stats *eth_stats) @@ -155 +156 @@ -@@ -1550,5 +1545,5 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct r= te_eth_stats *eth_stats) +@@ -1547,5 +1542,5 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct r= te_eth_stats *eth_stats) @@ -162 +163 @@ -@@ -1567,16 +1562,16 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct= rte_eth_stats *eth_stats) +@@ -1564,16 +1559,16 @@ qede_get_stats(struct rte_eth_dev *eth_dev, struct= rte_eth_stats *eth_stats) @@ -213 +214 @@ -@@ -1939,5 +1932,6 @@ qede_dev_supported_ptypes_get(struct rte_eth_dev *et= h_dev) +@@ -1938,5 +1931,6 @@ qede_dev_supported_ptypes_get(struct rte_eth_dev *et= h_dev) @@ -221 +222 @@ -@@ -2006,5 +2000,5 @@ int qede_rss_hash_update(struct rte_eth_dev *eth_dev= , +@@ -2005,5 +1999,5 @@ int qede_rss_hash_update(struct rte_eth_dev *eth_dev= , @@ -228 +229 @@ -@@ -2258,5 +2252,5 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uin= t16_t mtu) +@@ -2257,5 +2251,5 @@ static int qede_set_mtu(struct rte_eth_dev *dev, uin= t16_t mtu) @@ -235 +236 @@ -@@ -2287,7 +2281,11 @@ static int qede_set_mtu(struct rte_eth_dev *dev, ui= nt16_t mtu) +@@ -2286,7 +2280,11 @@ static int qede_set_mtu(struct rte_eth_dev *dev, ui= nt16_t mtu) @@ -250 +251 @@ -@@ -2430,8 +2428,4 @@ static int qede_common_dev_init(struct rte_eth_dev *= eth_dev, bool is_vf) +@@ -2429,8 +2427,4 @@ static int qede_common_dev_init(struct rte_eth_dev *= eth_dev, bool is_vf) @@ -259 +260 @@ -@@ -2491,4 +2485,14 @@ static int qede_common_dev_init(struct rte_eth_dev = *eth_dev, bool is_vf) +@@ -2490,4 +2484,14 @@ static int qede_common_dev_init(struct rte_eth_dev = *eth_dev, bool is_vf) @@ -275 +276 @@ -index d0e7c70be..5549d0bf3 100644 +index c06274d94..735dfdb66 100644 @@ -294 +295 @@ -index b3f62e0dd..81509f04b 100644 +index 0beade6d5..56ec91272 100644 @@ -304 +305 @@ -@@ -1346,5 +1346,4 @@ qede_flow_parse_actions(struct rte_eth_dev *dev, +@@ -1344,5 +1344,4 @@ qede_flow_parse_actions(struct rte_eth_dev *dev, @@ -310 +311 @@ -@@ -1361,5 +1360,5 @@ qede_flow_parse_actions(struct rte_eth_dev *dev, +@@ -1359,5 +1358,5 @@ qede_flow_parse_actions(struct rte_eth_dev *dev, @@ -318 +319 @@ -index cb8ac9bf6..dbb74fc64 100644 +index 64fd9e063..ca1305f1b 100644 @@ -529 +530 @@ -@@ -1742,4 +1816,21 @@ next_cqe: +@@ -1740,4 +1814,21 @@ next_cqe: @@ -551 +552 @@ -@@ -2264,4 +2355,22 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pk= ts, uint16_t nb_pkts) +@@ -2262,4 +2353,22 @@ qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pk= ts, uint16_t nb_pkts) @@ -575 +576 @@ -index 41a5f0f5c..75cc930fd 100644 +index 5b249cbb2..4a1435663 100644