From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9F3A3A04F3 for ; Fri, 6 Dec 2019 08:52:28 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 42EB41BF9F; Fri, 6 Dec 2019 08:52:28 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id AFF8D1BF7B; Fri, 6 Dec 2019 08:52:24 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Dec 2019 23:52:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,283,1571727600"; d="scan'208";a="219375090" Received: from intel.sh.intel.com ([10.239.255.32]) by fmsmga001.fm.intel.com with ESMTP; 05 Dec 2019 23:52:20 -0800 From: Guinan Sun To: dev@dpdk.org Cc: Beilei Xing , Qi Zhang , Qiming Yang , Guinan Sun , stable@dpdk.org Date: Fri, 6 Dec 2019 15:41:18 +0000 Message-Id: <20191206154118.4401-1-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-stable] [PATCH] net/i40e: fix flow control broken X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Repeat switching flow control on or off during receiving traffic, testpmd reports "failed to switch Tx queue occurs" after quit. The patch fixes the issue. Fixes: f53577f06925 ("i40e: support flow control") Cc: stable@dpdk.org Signed-off-by: Guinan Sun --- drivers/net/i40e/i40e_ethdev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 5999c964b..5507f6c39 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -53,7 +53,7 @@ /* Wait count and interval */ #define I40E_CHK_Q_ENA_COUNT 1000 -#define I40E_CHK_Q_ENA_INTERVAL_US 1000 +#define I40E_CHK_Q_ENA_INTERVAL_US 50000 /* Maximun number of VSI */ #define I40E_MAX_NUM_VSIS (384UL) -- 2.17.1