From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 84C2EA0525 for ; Sat, 1 Feb 2020 14:13:12 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5FC811C0D7; Sat, 1 Feb 2020 14:13:12 +0100 (CET) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 204261C0C3; Sat, 1 Feb 2020 14:13:08 +0100 (CET) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Feb 2020 05:13:08 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,390,1574150400"; d="scan'208";a="218886849" Received: from yexl-server.sh.intel.com (HELO localhost) ([10.67.117.17]) by orsmga007.jf.intel.com with ESMTP; 01 Feb 2020 05:13:06 -0800 Date: Sat, 1 Feb 2020 21:12:15 +0800 From: Ye Xiaolong To: Guinan Sun Cc: dev@dpdk.org, Wenzhuo Lu , Qiming Yang , Qi Zhang , stable@dpdk.org Message-ID: <20200201131215.GE54838@intel.com> References: <20191219044356.30762-1-guinanx.sun@intel.com> <20191219101758.24608-1-guinanx.sun@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191219101758.24608-1-guinanx.sun@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-stable] [dpdk-dev] [PATCH v2] net/ixgbe: fix flow ctrl mode setting X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, Guinan On 12/19, Guinan Sun wrote: >When the port starts, the hw register is reset first, >and then the required parameters are set again. >If the parameters to be used are not set after resetting the register, >a read register error will occur. This patch is used to fix the problem. > >Fixes: af75078fece3 ("first public release") >Cc: stable@dpdk.org > >Signed-off-by: Guinan Sun >--- >v2: changes >* Modify the initial value of requested_mode and current_mode >--- > drivers/net/ixgbe/ixgbe_ethdev.c | 24 ++++++++++++++++++++++-- > drivers/net/ixgbe/ixgbe_ethdev.h | 1 + > 2 files changed, 23 insertions(+), 2 deletions(-) > >diff --git a/drivers/net/ixgbe/ixgbe_ethdev.c b/drivers/net/ixgbe/ixgbe_ethdev.c >index 2c6fd0f13..573117e3a 100644 >--- a/drivers/net/ixgbe/ixgbe_ethdev.c >+++ b/drivers/net/ixgbe/ixgbe_ethdev.c >@@ -1170,8 +1170,8 @@ eth_ixgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) > memset(dcb_config, 0, sizeof(struct ixgbe_dcb_config)); > ixgbe_dcb_init(hw, dcb_config); > /* Get Hardware Flow Control setting */ >- hw->fc.requested_mode = ixgbe_fc_full; >- hw->fc.current_mode = ixgbe_fc_full; >+ hw->fc.requested_mode = ixgbe_fc_none; >+ hw->fc.current_mode = ixgbe_fc_none; > hw->fc.pause_time = IXGBE_FC_PAUSE; > for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { > hw->fc.low_water[i] = IXGBE_FC_LO; >@@ -2539,6 +2539,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev) > { > struct ixgbe_hw *hw = > IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private); >+ struct ixgbe_adapter *adapter = dev->data->dev_private; > struct ixgbe_vf_info *vfinfo = > *IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private); > struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); >@@ -2555,6 +2556,7 @@ ixgbe_dev_start(struct rte_eth_dev *dev) > IXGBE_DEV_PRIVATE_TO_TM_CONF(dev->data->dev_private); > struct ixgbe_macsec_setting *macsec_setting = > IXGBE_DEV_PRIVATE_TO_MACSEC_SETTING(dev->data->dev_private); >+ uint32_t mflcn; > > PMD_INIT_FUNC_TRACE(); > >@@ -2665,6 +2667,20 @@ ixgbe_dev_start(struct rte_eth_dev *dev) > } > > ixgbe_restore_statistics_mapping(dev); >+ err = ixgbe_fc_enable(hw); >+ if ((err == IXGBE_SUCCESS) || (err == IXGBE_ERR_FC_NOT_NEGOTIATED)) { >+ >+ mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); >+ >+ /* set or clear MFLCN.PMCF bit depending on configuration */ >+ if (adapter->mac_ctrl_frame_fwd != 0) >+ mflcn |= IXGBE_MFLCN_PMCF; >+ else >+ mflcn &= ~IXGBE_MFLCN_PMCF; >+ >+ IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn); >+ IXGBE_WRITE_FLUSH(hw); >+ } It'd be better to wrap above lines of code into a function to avoid duplication. Thanks, Xiaolong > > err = ixgbe_dev_rxtx_start(dev); > if (err < 0) { >@@ -2893,6 +2909,8 @@ ixgbe_dev_stop(struct rte_eth_dev *dev) > > adapter->rss_reta_updated = 0; > >+ adapter->mac_ctrl_frame_fwd = 0; >+ > hw->adapter_stopped = true; > } > >@@ -4646,6 +4664,7 @@ static int > ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) > { > struct ixgbe_hw *hw; >+ struct ixgbe_adapter *adapter = dev->data->dev_private; > int err; > uint32_t rx_buf_size; > uint32_t max_high_water; >@@ -4682,6 +4701,7 @@ ixgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) > hw->fc.low_water[0] = fc_conf->low_water; > hw->fc.send_xon = fc_conf->send_xon; > hw->fc.disable_fc_autoneg = !fc_conf->autoneg; >+ adapter->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; > > err = ixgbe_fc_enable(hw); > >diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h >index 76a1b9d18..5af584f9e 100644 >--- a/drivers/net/ixgbe/ixgbe_ethdev.h >+++ b/drivers/net/ixgbe/ixgbe_ethdev.h >@@ -510,6 +510,7 @@ struct ixgbe_adapter { > * mailbox status) link status. > */ > uint8_t pflink_fullchk; >+ uint8_t mac_ctrl_frame_fwd; > }; > > struct ixgbe_vf_representor { >-- >2.17.1 >