From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B07EAA0093 for ; Tue, 19 May 2020 15:06:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A7B361D603; Tue, 19 May 2020 15:06:48 +0200 (CEST) Received: from mail-wr1-f65.google.com (mail-wr1-f65.google.com [209.85.221.65]) by dpdk.org (Postfix) with ESMTP id 640B21D642 for ; Tue, 19 May 2020 15:06:47 +0200 (CEST) Received: by mail-wr1-f65.google.com with SMTP id y3so15869589wrt.1 for ; Tue, 19 May 2020 06:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X9WLSENkVZvMQu3wLZc3DCKiR4xFzNHnrpb3XFCsI+M=; b=GPt2OamE4FrRBF3V9VZUXfcYlcitYhdLQ1ugWADuVw7Ujf1LpWu2dN4om4lTTG0G0p I3JK2d9UlpFNZIVGu2Jg3D+w+QIi0hpHRSuA0+3Y6/tNca0/nrq4dAoKJXgDXPEciBWD VxiSyBnp3B29KFipf5N0sepovaYLj+U7xstYJUNbw/cYp8W+enVSdqwpIKbtzuY6jEvx 2Py5/7CBrHh2GQ6RvKe66bjojkBzj2WX/cnqrpVF71AOtNafdmyaoL8b5x7cCAX8NwWH 7oOBwloodGjrUMkVVheF2oFbNr0tpcJMrnytP2elJ9DiPg8571SGTnUqnfSTzXiCoPBt I1gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X9WLSENkVZvMQu3wLZc3DCKiR4xFzNHnrpb3XFCsI+M=; b=npu33wVbYzkcDLUt08Wg70RPJnHkMMnfg1m7jWobp3ihiIfZuTofQI6yLoGxVyRKM0 bkWIcNyHi3sUVD3wLmy2qCiriBJed2RpkQ1Fz1OX06Ep25zILJV6K01QweWAohp0SvoO 7FDKkan/P9Dc6+zeY30xqYC8SK1EB/dJJxhmbW2qqO+mPuz4NdqGN5z4K2G9OZnYwRQu K7qrX+3M+l9FJCdVSyfmxAB8yqO20FDS9ws+wRL5x6bAENPbK7C+KvPdoXh8uCKIEfVh bCiA6F7SP3g7XHR/Y6JnabxyCxZ/q6PJ2y2mGPyuSsfDpS7vaQigKhkmY9Uy3yjrqxEu pb5g== X-Gm-Message-State: AOAM533BpAOFzEYxCSesOaZjxBlc2KBnYD65ABqcqK0kA5gSlqWgxkbi apLhGgKRPe2kIynKyNNxsnE= X-Google-Smtp-Source: ABdhPJyDt18F1cb56XdbaQpgzDGEb8dYzr8g1b5pLiq1K7+9Y5BIlRBaszsywyXrRYzraTPM+Lz0VA== X-Received: by 2002:a5d:6443:: with SMTP id d3mr26389500wrw.5.1589893607065; Tue, 19 May 2020 06:06:47 -0700 (PDT) Received: from localhost ([88.98.246.218]) by smtp.gmail.com with ESMTPSA id v126sm4079495wmb.4.2020.05.19.06.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 May 2020 06:06:46 -0700 (PDT) From: luca.boccassi@gmail.com To: Qi Zhang Cc: Ben Shelton , Paul M Stillwell Jr , Qiming Yang , dpdk stable Date: Tue, 19 May 2020 14:02:31 +0100 Message-Id: <20200519130549.112823-16-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200519130549.112823-1-luca.boccassi@gmail.com> References: <20200519125804.104349-1-luca.boccassi@gmail.com> <20200519130549.112823-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] patch 'net/ice/base: read PSM clock frequency from register' has been queued to stable release 19.11.3 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 19.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/21/20. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Thanks. Luca Boccassi --- >From b97902938a3096713bf73564ec723bc58ac62daf Mon Sep 17 00:00:00 2001 From: Qi Zhang Date: Mon, 23 Mar 2020 15:17:27 +0800 Subject: [PATCH] net/ice/base: read PSM clock frequency from register [ upstream commit 76ac9d771c97cdba45339558e124c9244f211d04 ] Read the GLGEN_CLKSTAT_SRC register to determine which PSM clock frequency is selected. This ensures that the rate limiter profile calculations will be correct. Fixes: 453d087ccaff ("net/ice/base: add common functions") Signed-off-by: Ben Shelton Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang Acked-by: Qiming Yang --- drivers/net/ice/base/ice_common.c | 1 + drivers/net/ice/base/ice_sched.c | 57 +++++++++++++++++++++++++++---- drivers/net/ice/base/ice_sched.h | 7 +++- drivers/net/ice/base/ice_type.h | 4 ++- 4 files changed, 60 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 2646a96321..8006c5d689 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -674,6 +674,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw) "Failed to get scheduler allocated resources\n"); goto err_unroll_alloc; } + ice_sched_get_psm_clk_freq(hw); /* Initialize port_info struct with scheduler data */ status = ice_sched_init_port(hw->port_info); diff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c index 553fc28ff3..740f7c3ffa 100644 --- a/drivers/net/ice/base/ice_sched.c +++ b/drivers/net/ice/base/ice_sched.c @@ -1368,6 +1368,46 @@ sched_query_out: return status; } +/** + * ice_sched_get_psm_clk_freq - determine the PSM clock frequency + * @hw: pointer to the HW struct + * + * Determine the PSM clock frequency and store in HW struct + */ +void ice_sched_get_psm_clk_freq(struct ice_hw *hw) +{ + u32 val, clk_src; + + val = rd32(hw, GLGEN_CLKSTAT_SRC); + clk_src = (val & GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M) >> + GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S; + +#define PSM_CLK_SRC_367_MHZ 0x0 +#define PSM_CLK_SRC_416_MHZ 0x1 +#define PSM_CLK_SRC_446_MHZ 0x2 +#define PSM_CLK_SRC_390_MHZ 0x3 + + switch (clk_src) { + case PSM_CLK_SRC_367_MHZ: + hw->psm_clk_freq = ICE_PSM_CLK_367MHZ_IN_HZ; + break; + case PSM_CLK_SRC_416_MHZ: + hw->psm_clk_freq = ICE_PSM_CLK_416MHZ_IN_HZ; + break; + case PSM_CLK_SRC_446_MHZ: + hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; + break; + case PSM_CLK_SRC_390_MHZ: + hw->psm_clk_freq = ICE_PSM_CLK_390MHZ_IN_HZ; + break; + default: + ice_debug(hw, ICE_DBG_SCHED, "PSM clk_src unexpected %u\n", + clk_src); + /* fall back to a safe default */ + hw->psm_clk_freq = ICE_PSM_CLK_446MHZ_IN_HZ; + } +} + /** * ice_sched_find_node_in_subtree - Find node in part of base node subtree * @hw: pointer to the HW struct @@ -3671,11 +3711,12 @@ exit_cfg_agg_bw_alloc: /** * ice_sched_calc_wakeup - calculate RL profile wakeup parameter + * @hw: pointer to the HW struct * @bw: bandwidth in Kbps * * This function calculates the wakeup parameter of RL profile. */ -static u16 ice_sched_calc_wakeup(s32 bw) +static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw) { s64 bytes_per_sec, wakeup_int, wakeup_a, wakeup_b, wakeup_f; s32 wakeup_f_int; @@ -3683,7 +3724,7 @@ static u16 ice_sched_calc_wakeup(s32 bw) /* Get the wakeup integer value */ bytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE); - wakeup_int = DIV_64BIT(ICE_RL_PROF_FREQUENCY, bytes_per_sec); + wakeup_int = DIV_64BIT(hw->psm_clk_freq, bytes_per_sec); if (wakeup_int > 63) { wakeup = (u16)((1 << 15) | wakeup_int); } else { @@ -3692,7 +3733,7 @@ static u16 ice_sched_calc_wakeup(s32 bw) */ wakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int; wakeup_a = DIV_64BIT((s64)ICE_RL_PROF_MULTIPLIER * - ICE_RL_PROF_FREQUENCY, bytes_per_sec); + hw->psm_clk_freq, bytes_per_sec); /* Get Fraction value */ wakeup_f = wakeup_a - wakeup_b; @@ -3712,13 +3753,15 @@ static u16 ice_sched_calc_wakeup(s32 bw) /** * ice_sched_bw_to_rl_profile - convert BW to profile parameters + * @hw: pointer to the HW struct * @bw: bandwidth in Kbps * @profile: profile parameters to return * * This function converts the BW to profile structure format. */ static enum ice_status -ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile) +ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw, + struct ice_aqc_rl_profile_elem *profile) { enum ice_status status = ICE_ERR_PARAM; s64 bytes_per_sec, ts_rate, mv_tmp; @@ -3738,7 +3781,7 @@ ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile) for (i = 0; i < 64; i++) { u64 pow_result = BIT_ULL(i); - ts_rate = DIV_64BIT((s64)ICE_RL_PROF_FREQUENCY, + ts_rate = DIV_64BIT((s64)hw->psm_clk_freq, pow_result * ICE_RL_PROF_TS_MULTIPLIER); if (ts_rate <= 0) continue; @@ -3762,7 +3805,7 @@ ice_sched_bw_to_rl_profile(u32 bw, struct ice_aqc_rl_profile_elem *profile) if (found) { u16 wm; - wm = ice_sched_calc_wakeup(bw); + wm = ice_sched_calc_wakeup(hw, bw); profile->rl_multiply = CPU_TO_LE16(mv); profile->wake_up_calc = CPU_TO_LE16(wm); profile->rl_encode = CPU_TO_LE16(encode); @@ -3831,7 +3874,7 @@ ice_sched_add_rl_profile(struct ice_port_info *pi, if (!rl_prof_elem) return NULL; - status = ice_sched_bw_to_rl_profile(bw, &rl_prof_elem->profile); + status = ice_sched_bw_to_rl_profile(hw, bw, &rl_prof_elem->profile); if (status != ICE_SUCCESS) goto exit_add_rl_prof; diff --git a/drivers/net/ice/base/ice_sched.h b/drivers/net/ice/base/ice_sched.h index d6b467477c..1a8549931f 100644 --- a/drivers/net/ice/base/ice_sched.h +++ b/drivers/net/ice/base/ice_sched.h @@ -25,12 +25,16 @@ ((BIT(11) - 1) * 64) /* In Bytes */ #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED -#define ICE_RL_PROF_FREQUENCY 446000000 #define ICE_RL_PROF_ACCURACY_BYTES 128 #define ICE_RL_PROF_MULTIPLIER 10000 #define ICE_RL_PROF_TS_MULTIPLIER 32 #define ICE_RL_PROF_FRACTION 512 +#define ICE_PSM_CLK_367MHZ_IN_HZ 367647059 +#define ICE_PSM_CLK_416MHZ_IN_HZ 416666667 +#define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 +#define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 + struct rl_profile_params { u32 bw; /* in Kbps */ u16 rl_multiplier; @@ -83,6 +87,7 @@ ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, u16 *elems_ret, struct ice_sq_cd *cd); enum ice_status ice_sched_init_port(struct ice_port_info *pi); enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw); +void ice_sched_get_psm_clk_freq(struct ice_hw *hw); /* Functions to cleanup scheduler SW DB */ void ice_sched_clear_port(struct ice_port_info *pi); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index a8e4229a19..8b29e519d8 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -528,7 +528,7 @@ struct ice_sched_node { #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ LE16_TO_CPU((x)->info.eir_bw.bw_alloc) -struct ice_sched_rl_profle { +struct ice_sched_rl_profile { u32 rate; /* In Kbps */ struct ice_aqc_rl_profile_elem info; }; @@ -745,6 +745,8 @@ struct ice_hw { struct ice_sched_rl_profile **cir_profiles; struct ice_sched_rl_profile **eir_profiles; struct ice_sched_rl_profile **srl_profiles; + /* PSM clock frequency for calculating RL profile params */ + u32 psm_clk_freq; u64 debug_mask; /* BITMAP for debug mask */ enum ice_mac_type mac_type; -- 2.20.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2020-05-19 14:04:45.232311966 +0100 +++ 0016-net-ice-base-read-PSM-clock-frequency-from-register.patch 2020-05-19 14:04:44.096646197 +0100 @@ -1,14 +1,15 @@ -From 76ac9d771c97cdba45339558e124c9244f211d04 Mon Sep 17 00:00:00 2001 +From b97902938a3096713bf73564ec723bc58ac62daf Mon Sep 17 00:00:00 2001 From: Qi Zhang Date: Mon, 23 Mar 2020 15:17:27 +0800 Subject: [PATCH] net/ice/base: read PSM clock frequency from register +[ upstream commit 76ac9d771c97cdba45339558e124c9244f211d04 ] + Read the GLGEN_CLKSTAT_SRC register to determine which PSM clock frequency is selected. This ensures that the rate limiter profile calculations will be correct. Fixes: 453d087ccaff ("net/ice/base: add common functions") -Cc: stable@dpdk.org Signed-off-by: Ben Shelton Signed-off-by: Paul M Stillwell Jr @@ -22,10 +23,10 @@ 4 files changed, 60 insertions(+), 9 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c -index 786e99d210..9ef1aeef2c 100644 +index 2646a96321..8006c5d689 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c -@@ -672,6 +672,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw) +@@ -674,6 +674,7 @@ enum ice_status ice_init_hw(struct ice_hw *hw) "Failed to get scheduler allocated resources\n"); goto err_unroll_alloc; } @@ -191,10 +192,10 @@ /* Functions to cleanup scheduler SW DB */ void ice_sched_clear_port(struct ice_port_info *pi); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h -index 9773a549f2..237220ee8c 100644 +index a8e4229a19..8b29e519d8 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h -@@ -524,7 +524,7 @@ struct ice_sched_node { +@@ -528,7 +528,7 @@ struct ice_sched_node { #define ICE_TXSCHED_GET_EIR_BWALLOC(x) \ LE16_TO_CPU((x)->info.eir_bw.bw_alloc) @@ -203,7 +204,7 @@ u32 rate; /* In Kbps */ struct ice_aqc_rl_profile_elem info; }; -@@ -741,6 +741,8 @@ struct ice_hw { +@@ -745,6 +745,8 @@ struct ice_hw { struct ice_sched_rl_profile **cir_profiles; struct ice_sched_rl_profile **eir_profiles; struct ice_sched_rl_profile **srl_profiles;