From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 43C51A04DD for ; Thu, 22 Oct 2020 07:58:04 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0ED2472F1; Thu, 22 Oct 2020 07:58:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 685FF72F1 for ; Thu, 22 Oct 2020 07:58:01 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 09M5fRRL028920 for ; Wed, 21 Oct 2020 22:57:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Z6IM7yEsjr663LhBRmY2R8MHOP3d2CRYV/gXy2CtxkI=; b=Y3JdjtP5t2bp8agTi2FeODNfIn06H+7izJM56/zfp8pgiwFSt7j7lSMY52SSmiDoPC0l c6k4n8C/v6nkmLSsQN2aT3g9+9wisx5wFKodz6ZYrkp/GLRpWt0UEK6FyBbVDZa6t4TD X101not2E0Gp5PPGtVS9EbN/y8VYJuo8g6u3TzxiBBqNi7aZvZMVGBYCVJ/tYQf7lLh8 82cubid5lBnc8gOPQT+9T3A5x/taYi/JjbsJf1Uf4Ae54Tz+3/PtA09ibXTTSr90JiiP d8uozl2rdhZ8zocwTNs/Rk8J1odYaZ2JS3B7X/HfMq+ENuE+dEy7Hy+J4ysCXwx+6FA7 Qw== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0b-0016f401.pphosted.com with ESMTP id 34asbf23xb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Wed, 21 Oct 2020 22:57:59 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 21 Oct 2020 22:57:58 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 21 Oct 2020 22:57:57 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 21 Oct 2020 22:57:58 -0700 Received: from hyd1349.t110.caveonetworks.com (unknown [10.29.45.13]) by maili.marvell.com (Postfix) with ESMTP id 7026A3F703F; Wed, 21 Oct 2020 22:57:56 -0700 (PDT) From: Ankur Dwivedi To: CC: Ankur Dwivedi , Narayana Prasad Raju Athreya , Anoob Joseph Date: Thu, 22 Oct 2020 11:27:21 +0530 Message-ID: <20201022055721.3267-1-adwivedi@marvell.com> X-Mailer: git-send-email 2.28.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.737 definitions=2020-10-22_02:2020-10-20, 2020-10-22 signatures=0 Subject: [dpdk-stable] [PATCH 19.11] crypto/octeontx2: fix for multi process X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" During crypto device probe few functions should be called only for the primary process. This patch fixes this issue. Fixes: 818d138bcce9 ("crypto/octeontx2: add init sequence in probe") Signed-off-by: Ankur Dwivedi Reviewed-by: Narayana Prasad Raju Athreya Reviewed-by: Anoob Joseph --- drivers/crypto/octeontx2/otx2_cryptodev.c | 46 +++++++++++-------- drivers/crypto/octeontx2/otx2_cryptodev.h | 2 + drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 13 ++++-- 3 files changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.c b/drivers/crypto/octeontx2/otx2_cryptodev.c index 417eda6de..4626e754e 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev.c @@ -70,31 +70,34 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, otx2_dev = &vf->otx2_dev; - /* Initialize the base otx2_dev object */ - ret = otx2_dev_init(pci_dev, otx2_dev); - if (ret) { - CPT_LOG_ERR("Could not initialize otx2_dev"); - goto pmd_destroy; - } + if (rte_eal_process_type() == RTE_PROC_PRIMARY) { + /* Initialize the base otx2_dev object */ + ret = otx2_dev_init(pci_dev, otx2_dev); + if (ret) { + CPT_LOG_ERR("Could not initialize otx2_dev"); + goto pmd_destroy; + } - /* Get number of queues available on the device */ - ret = otx2_cpt_available_queues_get(dev, &nb_queues); - if (ret) { - CPT_LOG_ERR("Could not determine the number of queues available"); - goto otx2_dev_fini; - } + /* Get number of queues available on the device */ + ret = otx2_cpt_available_queues_get(dev, &nb_queues); + if (ret) { + CPT_LOG_ERR("Could not determine the number of queues available"); + goto otx2_dev_fini; + } - /* Don't exceed the limits set per VF */ - nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF); + /* Don't exceed the limits set per VF */ + nb_queues = RTE_MIN(nb_queues, OTX2_CPT_MAX_QUEUES_PER_VF); - if (nb_queues == 0) { - CPT_LOG_ERR("No free queues available on the device"); - goto otx2_dev_fini; - } + if (nb_queues == 0) { + CPT_LOG_ERR("No free queues available on the device"); + goto otx2_dev_fini; + } - vf->max_queues = nb_queues; + vf->max_queues = nb_queues; - CPT_LOG_INFO("Max queues supported by device: %d", vf->max_queues); + CPT_LOG_INFO("Max queues supported by device: %d", + vf->max_queues); + } dev->feature_flags = RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | @@ -105,6 +108,9 @@ otx2_cpt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_RSA_PRIV_OP_KEY_QT; + if (rte_eal_process_type() == RTE_PROC_SECONDARY) + otx2_cpt_set_enqdeq_fns(dev); + return 0; otx2_dev_fini: diff --git a/drivers/crypto/octeontx2/otx2_cryptodev.h b/drivers/crypto/octeontx2/otx2_cryptodev.h index c0aa661b3..17c0bee66 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev.h +++ b/drivers/crypto/octeontx2/otx2_cryptodev.h @@ -40,4 +40,6 @@ extern int otx2_cpt_logtype; */ extern uint8_t otx2_cryptodev_driver_id; +void otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev); + #endif /* _OTX2_CRYPTODEV_H_ */ diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index 65101b0d2..b87a16f30 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -808,6 +808,15 @@ otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) return nb_completed; } +void +otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev) +{ + dev->enqueue_burst = otx2_cpt_enqueue_burst; + dev->dequeue_burst = otx2_cpt_dequeue_burst; + + rte_mb(); +} + /* PMD ops */ static int @@ -857,10 +866,8 @@ otx2_cpt_dev_config(struct rte_cryptodev *dev, goto queues_detach; } - dev->enqueue_burst = otx2_cpt_enqueue_burst; - dev->dequeue_burst = otx2_cpt_dequeue_burst; + otx2_cpt_set_enqdeq_fns(dev); - rte_mb(); return 0; queues_detach: -- 2.28.0