From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A88BA04DD for ; Wed, 28 Oct 2020 11:52:41 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7BA2349E0; Wed, 28 Oct 2020 11:52:40 +0100 (CET) Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) by dpdk.org (Postfix) with ESMTP id 5058749E0 for ; Wed, 28 Oct 2020 11:52:39 +0100 (CET) Received: by mail-wm1-f49.google.com with SMTP id a72so4087142wme.5 for ; Wed, 28 Oct 2020 03:52:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CgVk0oJM/BUcCkxdSXIj9r2l1PCKkUbWjECS0nlEHeM=; b=Weyzn5W3bP28tAFMBN1AMIdXSmb5/hYMaddeqau6zhfaONnqemr4zK9iqCQVoMiC3G BTgHMFlHO4CA+5+L/EuZk7Rfld85aa+BfrHnyxvcqFyB0vnyYLnn53urQT8dsLaOZUUi NDiD86svnpWQQGOxrc9kfn+ypomL3OZh2KO4Xj4CA8CbpOuJ3pKmzGu+9d86XZTP6fmA mr7TZS1HvY8Zo1OpLpYntr93wRCOY0PZ6bn7Xe9UG8bbGTm688YEnYfnP1l1e18RdGGx EzQesD3LOslfbiLaFydqkXla5yq8La0Qa9h2o+ZzeuNOaV8ym07I0dx7+frh+tKcUdrA qacg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CgVk0oJM/BUcCkxdSXIj9r2l1PCKkUbWjECS0nlEHeM=; b=Arx3NJou8P5CA2Ts5UtqvlxNh/zhTMsn/mr7qg41W6sZPmM+vm6gtPrcVGCPjSNRZ1 yJ+y+f9z1sy48FdERSOIoKfy9O+aJudogb6CLtVqLcB0+nqfJdVJhxoyl6La5xtm1gsC OBZPTuJuuNGKBE9PkjkbKPueRKMqNGP1lUZV0k7KZ/xLX47a2DrBl2MWAJaUEDOChd9z 0KE0bq4sCte0Ml1QiddDfdTCqYdxmlnMSBdnQWtYU3mjEH5XjROXtsAOVfECK+Y7/Isn Kh+t8JaBr+orb1uaa5ubKpWTmIG6tqquA1wG98m2eRllknES1HbbMoRJUUeCQtZ9cGso KHdg== X-Gm-Message-State: AOAM530LFdLVE6aqhtmM7esx+YwAjtqiBPMc7CFOtjccEWisttWF0Ree 4uDj0HjV4gOHSr/tPQ2E4/72cU4bX/5pUlaX X-Google-Smtp-Source: ABdhPJy2DUP7GyYDP7V1Xl7UbQNdtxpvAoyA2cP4UU1wVGlgBCOLB/h11hmpjqrvjEA853Z6pw94Yg== X-Received: by 2002:a7b:c1d5:: with SMTP id a21mr3930837wmj.38.1603882358071; Wed, 28 Oct 2020 03:52:38 -0700 (PDT) Received: from localhost ([88.98.246.218]) by smtp.gmail.com with ESMTPSA id b190sm5905839wmd.35.2020.10.28.03.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2020 03:52:37 -0700 (PDT) From: luca.boccassi@gmail.com To: Hongbo Zheng Cc: Wei Hu , dpdk stable Date: Wed, 28 Oct 2020 10:44:40 +0000 Message-Id: <20201028104606.3504127-121-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201028104606.3504127-1-luca.boccassi@gmail.com> References: <20201028104606.3504127-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] patch 'net/hns3: check PCI config space reads' has been queued to stable release 19.11.6 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 19.11.6 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 10/30/20. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Thanks. Luca Boccassi --- >From dd2e679a4923c4f3e3b9ffc910ea909409e3ffaf Mon Sep 17 00:00:00 2001 From: Hongbo Zheng Date: Tue, 29 Sep 2020 20:01:16 +0800 Subject: [PATCH] net/hns3: check PCI config space reads [ upstream commit 243651cb6c8ca98ba7790d564f3d50cf9cd6c923 ] This patch add return value check when calling rte_pci_read_config function. Fixes: cea37e513329 ("net/hns3: fix FLR reset") Signed-off-by: Hongbo Zheng Signed-off-by: Wei Hu (Xavier) --- drivers/net/hns3/hns3_ethdev_vf.c | 62 +++++++++++++++++++++++++------ 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 87558832b2..5d1da44155 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -64,12 +64,18 @@ static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw, struct rte_ether_addr *mac_addr); /* set PCI bus mastering */ -static void +static int hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) { uint16_t reg; + int ret; - rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); + ret = rte_pci_read_config(device, ®, sizeof(reg), PCI_COMMAND); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_COMMAND); + return ret; + } if (op) /* set the master bit */ @@ -77,7 +83,7 @@ hns3vf_set_bus_master(const struct rte_pci_device *device, bool op) else reg &= ~(PCI_COMMAND_MASTER); - rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); + return rte_pci_write_config(device, ®, sizeof(reg), PCI_COMMAND); } /** @@ -94,16 +100,34 @@ hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) uint8_t pos; uint8_t id; int ttl; + int ret; + + ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS); + return 0; + } - rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS); if (!(status & PCI_STATUS_CAP_LIST)) return 0; ttl = MAX_PCIE_CAPABILITY; - rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST); + ret = rte_pci_read_config(device, &pos, sizeof(pos), + PCI_CAPABILITY_LIST); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + PCI_CAPABILITY_LIST); + return 0; + } + while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) { - rte_pci_read_config(device, &id, sizeof(id), - (pos + PCI_CAP_LIST_ID)); + ret = rte_pci_read_config(device, &id, sizeof(id), + (pos + PCI_CAP_LIST_ID)); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + (pos + PCI_CAP_LIST_ID)); + break; + } if (id == 0xFF) break; @@ -111,8 +135,13 @@ hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap) if (id == cap) return (int)pos; - rte_pci_read_config(device, &pos, sizeof(pos), - (pos + PCI_CAP_LIST_NEXT)); + ret = rte_pci_read_config(device, &pos, sizeof(pos), + (pos + PCI_CAP_LIST_NEXT)); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + (pos + PCI_CAP_LIST_NEXT)); + break; + } } return 0; } @@ -122,11 +151,18 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op) { uint16_t control; int pos; + int ret; pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX); if (pos) { - rte_pci_read_config(device, &control, sizeof(control), + ret = rte_pci_read_config(device, &control, sizeof(control), (pos + PCI_MSIX_FLAGS)); + if (ret < 0) { + PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", + (pos + PCI_MSIX_FLAGS)); + return -ENXIO; + } + if (op) control |= PCI_MSIX_FLAGS_ENABLE; else @@ -2110,7 +2146,11 @@ hns3vf_reinit_dev(struct hns3_adapter *hns) if (hw->reset.level == HNS3_VF_FULL_RESET) { rte_intr_disable(&pci_dev->intr_handle); - hns3vf_set_bus_master(pci_dev, true); + ret = hns3vf_set_bus_master(pci_dev, true); + if (ret) { + hns3_err(hw, "failed to set pci bus, ret = %d", ret); + return ret; + } } /* Firmware command initialize */ -- 2.20.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2020-10-28 10:35:15.506050445 +0000 +++ 0121-net-hns3-check-PCI-config-space-reads.patch 2020-10-28 10:35:11.680832615 +0000 @@ -1,13 +1,14 @@ -From 243651cb6c8ca98ba7790d564f3d50cf9cd6c923 Mon Sep 17 00:00:00 2001 +From dd2e679a4923c4f3e3b9ffc910ea909409e3ffaf Mon Sep 17 00:00:00 2001 From: Hongbo Zheng Date: Tue, 29 Sep 2020 20:01:16 +0800 Subject: [PATCH] net/hns3: check PCI config space reads +[ upstream commit 243651cb6c8ca98ba7790d564f3d50cf9cd6c923 ] + This patch add return value check when calling rte_pci_read_config function. Fixes: cea37e513329 ("net/hns3: fix FLR reset") -Cc: stable@dpdk.org Signed-off-by: Hongbo Zheng Signed-off-by: Wei Hu (Xavier) @@ -16,7 +17,7 @@ 1 file changed, 51 insertions(+), 11 deletions(-) diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c -index cf7ab2359d..1a19c0e6e6 100644 +index 87558832b2..5d1da44155 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -64,12 +64,18 @@ static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw, @@ -124,7 +125,7 @@ if (op) control |= PCI_MSIX_FLAGS_ENABLE; else -@@ -2576,7 +2612,11 @@ hns3vf_reinit_dev(struct hns3_adapter *hns) +@@ -2110,7 +2146,11 @@ hns3vf_reinit_dev(struct hns3_adapter *hns) if (hw->reset.level == HNS3_VF_FULL_RESET) { rte_intr_disable(&pci_dev->intr_handle);