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* [dpdk-stable] [PATCH 1/6] net/ena: fix getting xstats global stats offset
       [not found] <20201030113121.1310305-1-mk@semihalf.com>
@ 2020-10-30 11:31 ` Michal Krawczyk
  2020-10-30 11:31 ` [dpdk-stable] [PATCH 2/6] net/ena: fix setting Rx checksum flags in mbuf Michal Krawczyk
  2020-10-30 11:31 ` [dpdk-stable] [PATCH 4/6] net/ena/base: align IO cq allocation to a 4K Michal Krawczyk
  2 siblings, 0 replies; 3+ messages in thread
From: Michal Krawczyk @ 2020-10-30 11:31 UTC (permalink / raw)
  To: dev; +Cc: mw, igorch, gtzalik, Michal Krawczyk, stable

There was a bug in a code, which was reading stat_offset value from the
ena_stats_rx_strings array instead of ena_stats_global_strings.

It wasn't causing real problems just because ena_stats_rx_strings was
not smaller than ena_stats_global_strings and both arrays hold the same
offsets.

Fixes: 7830e905b7c9 ("net/ena: expose extended stats")
Cc: stable@dpdk.org

Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Reviewed-by: Igor Chauskin <igorch@amazon.com>
Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
---
 drivers/net/ena/ena_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index c513faf202..7ab9b93ba9 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -2724,7 +2724,7 @@ static int ena_xstats_get(struct rte_eth_dev *dev,
 		return 0;
 
 	for (stat = 0; stat < ENA_STATS_ARRAY_GLOBAL; stat++, count++) {
-		stat_offset = ena_stats_rx_strings[stat].stat_offset;
+		stat_offset = ena_stats_global_strings[stat].stat_offset;
 		stats_begin = &adapter->dev_stats;
 
 		xstats[count].id = count;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* [dpdk-stable] [PATCH 2/6] net/ena: fix setting Rx checksum flags in mbuf
       [not found] <20201030113121.1310305-1-mk@semihalf.com>
  2020-10-30 11:31 ` [dpdk-stable] [PATCH 1/6] net/ena: fix getting xstats global stats offset Michal Krawczyk
@ 2020-10-30 11:31 ` Michal Krawczyk
  2020-10-30 11:31 ` [dpdk-stable] [PATCH 4/6] net/ena/base: align IO cq allocation to a 4K Michal Krawczyk
  2 siblings, 0 replies; 3+ messages in thread
From: Michal Krawczyk @ 2020-10-30 11:31 UTC (permalink / raw)
  To: dev; +Cc: mw, igorch, gtzalik, Michal Krawczyk, stable

The driver was never setting PKT_RX_*_CKSUM_GOOD flags, so the only way
of checking if the checksum was checked was by testing for the
PKT_RX_*_CKSUM_BAD. In that situation, the application couldn't detect
if the checksum was valid or unknown, as unknown flag is equal to 0.

Moreover, the l3_csum_err value is only valid if the l3_proto is
indicating IPv4, so it shouldn't be checked for other protocols.

Fixes: 1173fca25af9 ("ena: add polling-mode driver")
Cc: stable@dpdk.org

Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Reviewed-by: Igor Chauskin <igorch@amazon.com>
Reviewed-by: Guy Tzalik <gtzalik@amazon.com>
---
 drivers/net/ena/ena_ethdev.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ena/ena_ethdev.c b/drivers/net/ena/ena_ethdev.c
index 7ab9b93ba9..ad593c882c 100644
--- a/drivers/net/ena/ena_ethdev.c
+++ b/drivers/net/ena/ena_ethdev.c
@@ -296,21 +296,23 @@ static inline void ena_rx_mbuf_prepare(struct rte_mbuf *mbuf,
 	else if (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)
 		packet_type |= RTE_PTYPE_L4_UDP;
 
-	if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4)
+	if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) {
 		packet_type |= RTE_PTYPE_L3_IPV4;
-	else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6)
+		if (unlikely(ena_rx_ctx->l3_csum_err))
+			ol_flags |= PKT_RX_IP_CKSUM_BAD;
+		else
+			ol_flags |= PKT_RX_IP_CKSUM_GOOD;
+	} else if (ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV6) {
 		packet_type |= RTE_PTYPE_L3_IPV6;
+	}
 
-	if (!ena_rx_ctx->l4_csum_checked)
+	if (!ena_rx_ctx->l4_csum_checked || ena_rx_ctx->frag)
 		ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
 	else
-		if (unlikely(ena_rx_ctx->l4_csum_err) && !ena_rx_ctx->frag)
+		if (unlikely(ena_rx_ctx->l4_csum_err))
 			ol_flags |= PKT_RX_L4_CKSUM_BAD;
 		else
-			ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN;
-
-	if (unlikely(ena_rx_ctx->l3_csum_err))
-		ol_flags |= PKT_RX_IP_CKSUM_BAD;
+			ol_flags |= PKT_RX_L4_CKSUM_GOOD;
 
 	mbuf->ol_flags = ol_flags;
 	mbuf->packet_type = packet_type;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

* [dpdk-stable] [PATCH 4/6] net/ena/base: align IO cq allocation to a 4K
       [not found] <20201030113121.1310305-1-mk@semihalf.com>
  2020-10-30 11:31 ` [dpdk-stable] [PATCH 1/6] net/ena: fix getting xstats global stats offset Michal Krawczyk
  2020-10-30 11:31 ` [dpdk-stable] [PATCH 2/6] net/ena: fix setting Rx checksum flags in mbuf Michal Krawczyk
@ 2020-10-30 11:31 ` Michal Krawczyk
  2 siblings, 0 replies; 3+ messages in thread
From: Michal Krawczyk @ 2020-10-30 11:31 UTC (permalink / raw)
  To: dev
  Cc: mw, igorch, gtzalik, Michal Krawczyk, stable, Ido Segev, Amit Bernstein

Latest generation HW requires IO completion queue descriptors to be
aligned to a 4K in order to achieve the best performance.

Because of that, the new allocation macros were added, which allows
driver to allocate the memory with specified alignemnt.

The previous allocation macros are now wrappers around the macros
doing the alignment, with the alignment value equal to cacheline size.

Fixes: b68309be44c0 ("net/ena/base: update communication layer for the ENAv2")
Cc: stable@dpdk.org

Signed-off-by: Ido Segev <idose@amazon.com>
Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Reviewed-by: Igor Chauskin <igorch@amazon.com>
Reviewed-by: Amit Bernstein <amitbern@amazon.com>
---
 drivers/net/ena/base/ena_com.c       | 26 ++++++++++----------
 drivers/net/ena/base/ena_com.h       |  2 ++
 drivers/net/ena/base/ena_plat_dpdk.h | 36 +++++++++++++++++++++-------
 3 files changed, 44 insertions(+), 20 deletions(-)

diff --git a/drivers/net/ena/base/ena_com.c b/drivers/net/ena/base/ena_com.c
index 3686ae05c4..aae68721fb 100644
--- a/drivers/net/ena/base/ena_com.c
+++ b/drivers/net/ena/base/ena_com.c
@@ -413,19 +413,21 @@ static int ena_com_init_io_cq(struct ena_com_dev *ena_dev,
 	size = io_cq->cdesc_entry_size_in_bytes * io_cq->q_depth;
 	io_cq->bus = ena_dev->bus;
 
-	ENA_MEM_ALLOC_COHERENT_NODE(ena_dev->dmadev,
-			size,
-			io_cq->cdesc_addr.virt_addr,
-			io_cq->cdesc_addr.phys_addr,
-			io_cq->cdesc_addr.mem_handle,
-			ctx->numa_node,
-			prev_node);
+	ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(ena_dev->dmadev,
+					    size,
+					    io_cq->cdesc_addr.virt_addr,
+					    io_cq->cdesc_addr.phys_addr,
+					    io_cq->cdesc_addr.mem_handle,
+					    ctx->numa_node,
+					    prev_node,
+					    ENA_CDESC_RING_SIZE_ALIGNMENT);
 	if (!io_cq->cdesc_addr.virt_addr) {
-		ENA_MEM_ALLOC_COHERENT(ena_dev->dmadev,
-				       size,
-				       io_cq->cdesc_addr.virt_addr,
-				       io_cq->cdesc_addr.phys_addr,
-				       io_cq->cdesc_addr.mem_handle);
+		ENA_MEM_ALLOC_COHERENT_ALIGNED(ena_dev->dmadev,
+					       size,
+					       io_cq->cdesc_addr.virt_addr,
+					       io_cq->cdesc_addr.phys_addr,
+					       io_cq->cdesc_addr.mem_handle,
+					       ENA_CDESC_RING_SIZE_ALIGNMENT);
 	}
 
 	if (!io_cq->cdesc_addr.virt_addr) {
diff --git a/drivers/net/ena/base/ena_com.h b/drivers/net/ena/base/ena_com.h
index 8eacaeab0e..64d8f247cb 100644
--- a/drivers/net/ena/base/ena_com.h
+++ b/drivers/net/ena/base/ena_com.h
@@ -23,6 +23,8 @@
 #define ADMIN_CQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_acq_entry))
 #define ADMIN_AENQ_SIZE(depth)	((depth) * sizeof(struct ena_admin_aenq_entry))
 
+#define ENA_CDESC_RING_SIZE_ALIGNMENT	(1 << 12) /* 4K */
+
 /*****************************************************************************/
 /*****************************************************************************/
 /* ENA adaptive interrupt moderation settings */
diff --git a/drivers/net/ena/base/ena_plat_dpdk.h b/drivers/net/ena/base/ena_plat_dpdk.h
index a6782f3732..48c77f0c19 100644
--- a/drivers/net/ena/base/ena_plat_dpdk.h
+++ b/drivers/net/ena/base/ena_plat_dpdk.h
@@ -172,7 +172,8 @@ do {                                                                   \
  */
 extern rte_atomic32_t ena_alloc_cnt;
 
-#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle)	\
+#define ENA_MEM_ALLOC_COHERENT_ALIGNED(					\
+	dmadev, size, virt, phys, handle, alignment)			\
 	do {								\
 		const struct rte_memzone *mz = NULL;			\
 		ENA_TOUCH(dmadev); ENA_TOUCH(handle);			\
@@ -181,9 +182,10 @@ extern rte_atomic32_t ena_alloc_cnt;
 			snprintf(z_name, sizeof(z_name),		\
 			 "ena_alloc_%d",				\
 			 rte_atomic32_add_return(&ena_alloc_cnt, 1));	\
-			mz = rte_memzone_reserve(z_name, size,		\
+			mz = rte_memzone_reserve_aligned(z_name, size,	\
 					SOCKET_ID_ANY,			\
-					RTE_MEMZONE_IOVA_CONTIG);	\
+					RTE_MEMZONE_IOVA_CONTIG,	\
+					alignment);			\
 			handle = mz;					\
 		}							\
 		if (mz == NULL) {					\
@@ -195,13 +197,21 @@ extern rte_atomic32_t ena_alloc_cnt;
 			phys = mz->iova;				\
 		}							\
 	} while (0)
+#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle)	\
+		ENA_MEM_ALLOC_COHERENT_ALIGNED(				\
+			dmadev,						\
+			size,						\
+			virt,						\
+			phys,						\
+			handle,						\
+			RTE_CACHE_LINE_SIZE)
 #define ENA_MEM_FREE_COHERENT(dmadev, size, virt, phys, handle) 	\
 		({ ENA_TOUCH(size); ENA_TOUCH(phys);			\
 		   ENA_TOUCH(dmadev);					\
 		   rte_memzone_free(handle); })
 
-#define ENA_MEM_ALLOC_COHERENT_NODE(					\
-	dmadev, size, virt, phys, mem_handle, node, dev_node)		\
+#define ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(				\
+	dmadev, size, virt, phys, mem_handle, node, dev_node, alignment) \
 	do {								\
 		const struct rte_memzone *mz = NULL;			\
 		ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);			\
@@ -210,8 +220,8 @@ extern rte_atomic32_t ena_alloc_cnt;
 			snprintf(z_name, sizeof(z_name),		\
 			 "ena_alloc_%d",				\
 			 rte_atomic32_add_return(&ena_alloc_cnt, 1));   \
-			mz = rte_memzone_reserve(z_name, size, node,	\
-				RTE_MEMZONE_IOVA_CONTIG);		\
+			mz = rte_memzone_reserve_aligned(z_name, size, node, \
+				RTE_MEMZONE_IOVA_CONTIG, alignment);	\
 			mem_handle = mz;				\
 		}							\
 		if (mz == NULL) {					\
@@ -223,7 +233,17 @@ extern rte_atomic32_t ena_alloc_cnt;
 			phys = mz->iova;				\
 		}							\
 	} while (0)
-
+#define ENA_MEM_ALLOC_COHERENT_NODE(					\
+	dmadev, size, virt, phys, mem_handle, node, dev_node)		\
+		ENA_MEM_ALLOC_COHERENT_NODE_ALIGNED(			\
+			dmadev,						\
+			size,						\
+			virt,						\
+			phys,						\
+			mem_handle,					\
+			node,						\
+			dev_node,					\
+			RTE_CACHE_LINE_SIZE)
 #define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \
 	do {								\
 		ENA_TOUCH(dmadev); ENA_TOUCH(dev_node);			\
-- 
2.25.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2020-10-30 11:31 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <20201030113121.1310305-1-mk@semihalf.com>
2020-10-30 11:31 ` [dpdk-stable] [PATCH 1/6] net/ena: fix getting xstats global stats offset Michal Krawczyk
2020-10-30 11:31 ` [dpdk-stable] [PATCH 2/6] net/ena: fix setting Rx checksum flags in mbuf Michal Krawczyk
2020-10-30 11:31 ` [dpdk-stable] [PATCH 4/6] net/ena/base: align IO cq allocation to a 4K Michal Krawczyk

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