From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 33B21A04B1 for ; Thu, 5 Nov 2020 13:41:23 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 1E1E2C80C; Thu, 5 Nov 2020 13:41:22 +0100 (CET) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by dpdk.org (Postfix) with ESMTP id A8568C808 for ; Thu, 5 Nov 2020 13:41:19 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1604580078; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dRjnTFACAJUq0Sxtmt1blT6uD+22n3Bq8rzXLKpHQTM=; b=hau9nwhqBkOeIldX30PKH5wP2wASN8+a/5Hk+fmjEMfdeRX7lzYtZIMsCU8Pu5NibntdFb A4JOdIf/11YengO3mydReGm3TZ6c7hPrhH+dt7eO1GFQ/8EXnYDcDGNkcgwMz1pHS319Hm GKsihp6CT8HPedP+MLit6A4Vz5WFiLs= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-574-R8alZ62nMCmj470fQi6D-g-1; Thu, 05 Nov 2020 07:41:14 -0500 X-MC-Unique: R8alZ62nMCmj470fQi6D-g-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 0F027186DD22; Thu, 5 Nov 2020 12:41:13 +0000 (UTC) Received: from rh.redhat.com (ovpn-113-249.ams2.redhat.com [10.36.113.249]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1B8FB57; Thu, 5 Nov 2020 12:41:11 +0000 (UTC) From: Kevin Traynor To: Junyu Jiang Cc: Ferruh Yigit , dpdk stable Date: Thu, 5 Nov 2020 12:39:31 +0000 Message-Id: <20201105124015.306404-24-ktraynor@redhat.com> In-Reply-To: <20201105124015.306404-1-ktraynor@redhat.com> References: <20201105124015.306404-1-ktraynor@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ktraynor@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII" Subject: [dpdk-stable] patch 'net/i40e: fix byte counters' has been queued to LTS release 18.11.11 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to LTS release 18.11.11 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/10/20. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/kevintraynor/dpdk-stable-queue This queued commit can be viewed at: https://github.com/kevintraynor/dpdk-stable-queue/commit/f494d5199c6978f98f889875f33c101d88e0c080 Thanks. Kevin. --- >From f494d5199c6978f98f889875f33c101d88e0c080 Mon Sep 17 00:00:00 2001 From: Junyu Jiang Date: Tue, 22 Sep 2020 09:19:31 +0000 Subject: [PATCH] net/i40e: fix byte counters [ upstream commit b96646187285b1b593b76af5dbcc365a99900377 ] This patch fixed the issue that rx/tx bytes statistics counters overflowed on 48 bit limitation by enlarging the limitation. Fixes: 4861cde46116 ("i40e: new poll mode driver") Signed-off-by: Junyu Jiang Reviewed-by: Ferruh Yigit --- doc/guides/nics/i40e.rst | 9 +++++ drivers/net/i40e/i40e_ethdev.c | 66 +++++++++++++++++++++------------- drivers/net/i40e/i40e_ethdev.h | 9 +++++ 3 files changed, 59 insertions(+), 25 deletions(-) diff --git a/doc/guides/nics/i40e.rst b/doc/guides/nics/i40e.rst index 01fa817a6d..b8f0b8b2f1 100644 --- a/doc/guides/nics/i40e.rst +++ b/doc/guides/nics/i40e.rst @@ -558,4 +558,13 @@ However, the Rx statistics, when calling `rte_eth_stats_get` incorrectly shows it as received. +RX/TX statistics may be incorrect when register overflowed +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The rx_bytes/tx_bytes statistics register is 48 bit length. +Although this limitation is enlarged to 64 bit length on the software side, +but there is no way to detect if the overflow occurred more than once. +So rx_bytes/tx_bytes statistics data is correct when statistics are +updated at least once between two overflows. + VF & TC max bandwidth setting ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 9aacb12293..bb750c0ccf 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -2825,4 +2825,19 @@ i40e_dev_link_update(struct rte_eth_dev *dev, } +static void +i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg, + uint32_t loreg, bool offset_loaded, uint64_t *offset, + uint64_t *stat, uint64_t *prev_stat) +{ + i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat); + /* enlarge the limitation when statistics counters overflowed */ + if (offset_loaded) { + if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat) + *stat += (uint64_t)1 << I40E_48_BIT_WIDTH; + *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat); + } + *prev_stat = *stat; +} + /* Get all the statistics of a VSI */ void @@ -2834,7 +2849,7 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx); - i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx), - vsi->offset_loaded, &oes->rx_bytes, - &nes->rx_bytes); + i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx), + vsi->offset_loaded, &oes->rx_bytes, + &nes->rx_bytes, &vsi->prev_rx_bytes); i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx), vsi->offset_loaded, &oes->rx_unicast, @@ -2857,7 +2872,7 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) &oes->rx_unknown_protocol, &nes->rx_unknown_protocol); - i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx), - vsi->offset_loaded, &oes->tx_bytes, - &nes->tx_bytes); + i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx), + vsi->offset_loaded, &oes->tx_bytes, + &nes->tx_bytes, &vsi->prev_tx_bytes); i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx), vsi->offset_loaded, &oes->tx_unicast, @@ -2901,15 +2916,16 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) /* Get rx/tx bytes of internal transfer packets */ - i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port), - I40E_GLV_GORCL(hw->port), - pf->offset_loaded, - &pf->internal_stats_offset.rx_bytes, - &pf->internal_stats.rx_bytes); - - i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port), - I40E_GLV_GOTCL(hw->port), - pf->offset_loaded, - &pf->internal_stats_offset.tx_bytes, - &pf->internal_stats.tx_bytes); + i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port), + I40E_GLV_GORCL(hw->port), + pf->offset_loaded, + &pf->internal_stats_offset.rx_bytes, + &pf->internal_stats.rx_bytes, + &pf->internal_prev_rx_bytes); + i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port), + I40E_GLV_GOTCL(hw->port), + pf->offset_loaded, + &pf->internal_stats_offset.tx_bytes, + &pf->internal_stats.tx_bytes, + &pf->internal_prev_tx_bytes); /* Get total internal rx packet count */ i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port), @@ -2951,8 +2967,8 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) /* Get statistics of struct i40e_eth_stats */ - i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port), - I40E_GLPRT_GORCL(hw->port), - pf->offset_loaded, &os->eth.rx_bytes, - &ns->eth.rx_bytes); + i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port), + I40E_GLPRT_GORCL(hw->port), + pf->offset_loaded, &os->eth.rx_bytes, + &ns->eth.rx_bytes, &pf->prev_rx_bytes); i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port), I40E_GLPRT_UPRCL(hw->port), @@ -3008,8 +3024,8 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) &os->eth.rx_unknown_protocol, &ns->eth.rx_unknown_protocol); - i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port), - I40E_GLPRT_GOTCL(hw->port), - pf->offset_loaded, &os->eth.tx_bytes, - &ns->eth.tx_bytes); + i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port), + I40E_GLPRT_GOTCL(hw->port), + pf->offset_loaded, &os->eth.tx_bytes, + &ns->eth.tx_bytes, &pf->prev_tx_bytes); i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port), I40E_GLPRT_UPTCL(hw->port), diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index d224a35020..6cec6cf0c1 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -272,4 +272,7 @@ enum i40e_flxpld_layer_idx { (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) +#define I40E_RXTX_BYTES_H_16_BIT(bytes) ((bytes) & ~I40E_48_BIT_MASK) +#define I40E_RXTX_BYTES_L_48_BIT(bytes) ((bytes) & I40E_48_BIT_MASK) + struct i40e_adapter; @@ -388,4 +391,6 @@ struct i40e_vsi { uint8_t vlan_filter_on; /* The VLAN filter enabled */ struct i40e_bw_info bw_info; /* VSI bandwidth information */ + uint64_t prev_rx_bytes; + uint64_t prev_tx_bytes; }; @@ -976,4 +981,8 @@ struct i40e_pf { /* Switch Domain Id */ uint16_t switch_domain_id; + uint64_t prev_rx_bytes; + uint64_t prev_tx_bytes; + uint64_t internal_prev_rx_bytes; + uint64_t internal_prev_tx_bytes; }; -- 2.26.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2020-11-05 12:38:54.701434585 +0000 +++ 0024-net-i40e-fix-byte-counters.patch 2020-11-05 12:38:54.195895985 +0000 @@ -1 +1 @@ -From b96646187285b1b593b76af5dbcc365a99900377 Mon Sep 17 00:00:00 2001 +From f494d5199c6978f98f889875f33c101d88e0c080 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit b96646187285b1b593b76af5dbcc365a99900377 ] + @@ -10 +11,0 @@ -Cc: stable@dpdk.org @@ -21 +22 @@ -index b7430f6c4e..a0b81e6695 100644 +index 01fa817a6d..b8f0b8b2f1 100644 @@ -24 +25 @@ -@@ -671,4 +671,13 @@ However, the Rx statistics, when calling `rte_eth_stats_get` incorrectly +@@ -558,4 +558,13 @@ However, the Rx statistics, when calling `rte_eth_stats_get` incorrectly @@ -39 +40 @@ -index 563f21d9df..6439baf2f8 100644 +index 9aacb12293..bb750c0ccf 100644 @@ -42 +43 @@ -@@ -3053,4 +3053,19 @@ i40e_dev_link_update(struct rte_eth_dev *dev, +@@ -2825,4 +2825,19 @@ i40e_dev_link_update(struct rte_eth_dev *dev, @@ -62 +63 @@ -@@ -3062,7 +3077,7 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) +@@ -2834,7 +2849,7 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) @@ -73 +74 @@ -@@ -3085,7 +3100,7 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) +@@ -2857,7 +2872,7 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi) @@ -84 +85 @@ -@@ -3129,15 +3144,16 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) +@@ -2901,15 +2916,16 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) @@ -112 +113 @@ -@@ -3179,8 +3195,8 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) +@@ -2951,8 +2967,8 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) @@ -125 +126 @@ -@@ -3237,8 +3253,8 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) +@@ -3008,8 +3024,8 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw) @@ -139 +140 @@ -index 19f821829a..1466998aa1 100644 +index d224a35020..6cec6cf0c1 100644 @@ -142,2 +143,2 @@ -@@ -283,4 +283,7 @@ struct rte_flow { - (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) +@@ -272,4 +272,7 @@ enum i40e_flxpld_layer_idx { + (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2) @@ -149,2 +150,2 @@ - struct rte_pci_driver; -@@ -400,4 +403,6 @@ struct i40e_vsi { + +@@ -388,4 +391,6 @@ struct i40e_vsi { @@ -157,3 +158,3 @@ -@@ -1157,4 +1162,8 @@ struct i40e_pf { - - struct i40e_vf_msg_cfg vf_msg_cfg; +@@ -976,4 +981,8 @@ struct i40e_pf { + /* Switch Domain Id */ + uint16_t switch_domain_id;