From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED72EA04DD for ; Fri, 20 Nov 2020 11:42:01 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 551E3C8B2; Fri, 20 Nov 2020 11:42:00 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id EFB20DED; Fri, 20 Nov 2020 11:41:56 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0AKAfGjs019051; Fri, 20 Nov 2020 02:41:55 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=mDI0mVfBAVfbYeZkmcOm2Cz8NtxHp7+ngV742jh4x/w=; b=a/dR8BoJPzS8P6mGC2UCH+KPT8KrKbE64pBxMwKv46mbpqObRiD9w2Ut7nyFcn82IQ9J Pe9tpZyC1OD8lsaXOqnc0ouHXL5E0fPQSVZAySn/7CiDZLchjBPtBdda8o1/qQEJdZiV xY5Q82s9sp7yhbMaF1qst5o34RAryNOGWgy5dRBBOpuF/TaC6Uqpq+8kMhJryfHjAiL/ 69Gff0YhT5buFZc7VOa4txdRmU2tHbffBSR8CQZmp0sE6OR2L4XZVJs1VDiIlSs2j51d nBVMD+P+0bdCkjxYyUcGr2NQiT0TI8rgbuET2GYKyUstaCT4Uit6zw3RYQIAh66CozJV 1g== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 34w7ncyrr2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 20 Nov 2020 02:41:55 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 20 Nov 2020 02:41:53 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 20 Nov 2020 02:41:52 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 20 Nov 2020 02:41:52 -0800 Received: from BG-LT7430.marvell.com (unknown [10.193.86.114]) by maili.marvell.com (Postfix) with ESMTP id D86C43F703F; Fri, 20 Nov 2020 02:41:50 -0800 (PST) From: To: , Pavan Nikhilesh CC: , Date: Fri, 20 Nov 2020 16:11:46 +0530 Message-ID: <20201120104147.1473-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201117164630.2971-1-pbhagavatula@marvell.com> References: <20201117164630.2971-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.312, 18.0.737 definitions=2020-11-20_04:2020-11-19, 2020-11-20 signatures=0 Subject: [dpdk-stable] [dpdk-dev] [PATCH v2] event/octeontx2: fix unconditional Tx flush X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" From: Pavan Nikhilesh Fix unconditional Tx flush, handle packet retransmit cases where flush has to be differed. Fixes: cb7ee83b6365 ("event/octeontx2: improve single flow performance") Cc: stable@dpdk.org Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_evdev.h | 1 + drivers/event/octeontx2/otx2_worker.c | 14 +++++++++----- drivers/event/octeontx2/otx2_worker.h | 20 +++++++++++++++----- 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/event/octeontx2/otx2_evdev.h b/drivers/event/octeontx2/otx2_evdev.h index 547e29d4a..49a865e6f 100644 --- a/drivers/event/octeontx2/otx2_evdev.h +++ b/drivers/event/octeontx2/otx2_evdev.h @@ -79,6 +79,7 @@ #define SSOW_LF_GWS_OP_GWC_INVAL (0xe00ull) #define OTX2_SSOW_GET_BASE_ADDR(_GW) ((_GW) - SSOW_LF_GWS_OP_GET_WORK) +#define OTX2_SSOW_TT_FROM_TAG(x) (((x) >> 32) & SSO_TT_EMPTY) #define NSEC2USEC(__ns) ((__ns) / 1E3) #define USEC2NSEC(__us) ((__us) * 1E3) diff --git a/drivers/event/octeontx2/otx2_worker.c b/drivers/event/octeontx2/otx2_worker.c index 1d427e4a3..b098407e0 100644 --- a/drivers/event/octeontx2/otx2_worker.c +++ b/drivers/event/octeontx2/otx2_worker.c @@ -274,12 +274,14 @@ otx2_ssogws_tx_adptr_enq_ ## name(void *port, struct rte_event ev[], \ { \ struct otx2_ssogws *ws = port; \ uint64_t cmd[sz]; \ + int i; \ \ - RTE_SET_USED(nb_events); \ - return otx2_ssogws_event_tx(ws, ev, cmd, (const uint64_t \ + for (i = 0; i < nb_events; i++) \ + otx2_ssogws_event_tx(ws, &ev[i], cmd, (const uint64_t \ (*)[RTE_MAX_QUEUES_PER_PORT]) \ &ws->tx_adptr_data, \ flags); \ + return nb_events; \ } SSO_TX_ADPTR_ENQ_FASTPATH_FUNC #undef T @@ -289,14 +291,16 @@ uint16_t __rte_hot \ otx2_ssogws_tx_adptr_enq_seg_ ## name(void *port, struct rte_event ev[],\ uint16_t nb_events) \ { \ - struct otx2_ssogws *ws = port; \ uint64_t cmd[(sz) + NIX_TX_MSEG_SG_DWORDS - 2]; \ + struct otx2_ssogws *ws = port; \ + int i; \ \ - RTE_SET_USED(nb_events); \ - return otx2_ssogws_event_tx(ws, ev, cmd, (const uint64_t \ + for (i = 0; i < nb_events; i++) \ + otx2_ssogws_event_tx(ws, &ev[i], cmd, (const uint64_t \ (*)[RTE_MAX_QUEUES_PER_PORT]) \ &ws->tx_adptr_data, \ (flags) | NIX_TX_MULTI_SEG_F); \ + return nb_events; \ } SSO_TX_ADPTR_ENQ_FASTPATH_FUNC #undef T diff --git a/drivers/event/octeontx2/otx2_worker.h b/drivers/event/octeontx2/otx2_worker.h index 3efd3ba97..0a7d6671c 100644 --- a/drivers/event/octeontx2/otx2_worker.h +++ b/drivers/event/octeontx2/otx2_worker.h @@ -198,6 +198,10 @@ otx2_ssogws_swtag_untag(struct otx2_ssogws *ws) static __rte_always_inline void otx2_ssogws_swtag_flush(struct otx2_ssogws *ws) { + if (OTX2_SSOW_TT_FROM_TAG(otx2_read64(ws->tag_op)) == SSO_TT_EMPTY) { + ws->cur_tt = SSO_SYNC_EMPTY; + return; + } otx2_write64(0, ws->swtag_flush_op); ws->cur_tt = SSO_SYNC_EMPTY; } @@ -272,13 +276,14 @@ otx2_ssogws_prepare_pkt(const struct otx2_eth_txq *txq, struct rte_mbuf *m, } static __rte_always_inline uint16_t -otx2_ssogws_event_tx(struct otx2_ssogws *ws, struct rte_event ev[], - uint64_t *cmd, const uint64_t - txq_data[][RTE_MAX_QUEUES_PER_PORT], +otx2_ssogws_event_tx(struct otx2_ssogws *ws, struct rte_event *ev, + uint64_t *cmd, + const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT], const uint32_t flags) { - struct rte_mbuf *m = ev[0].mbuf; + struct rte_mbuf *m = ev->mbuf; const struct otx2_eth_txq *txq; + uint16_t ref_cnt = m->refcnt; if ((flags & NIX_TX_OFFLOAD_SECURITY_F) && (m->ol_flags & PKT_TX_SEC_OFFLOAD)) { @@ -329,7 +334,12 @@ otx2_ssogws_event_tx(struct otx2_ssogws *ws, struct rte_event ev[], } } - otx2_write64(0, ws->swtag_flush_op); + if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) { + if (ref_cnt > 1) + return 1; + } + + otx2_ssogws_swtag_flush(ws); return 1; } -- 2.17.1