From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (xvm-189-124.dc0.ghst.net [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D5FD9A0524 for ; Fri, 8 Jan 2021 09:26:40 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B80D3140E53; Fri, 8 Jan 2021 09:26:40 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id D1754140E53; Fri, 8 Jan 2021 09:26:39 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5701C31B; Fri, 8 Jan 2021 00:26:39 -0800 (PST) Received: from net-arm-n1amp-01.shanghai.arm.com (net-arm-n1amp-01.shanghai.arm.com [10.169.208.220]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0C0713F70D; Fri, 8 Jan 2021 00:26:35 -0800 (PST) From: Ruifeng Wang To: Jerin Jacob , Nithin Dabilpuram , Pavan Nikhilesh Cc: dev@dpdk.org, vladimir.medvedkin@intel.com, hemant.agrawal@nxp.com, honnappa.nagarahalli@arm.com, nd@arm.com, Ruifeng Wang , stable@dpdk.org Date: Fri, 8 Jan 2021 08:25:22 +0000 Message-Id: <20210108082523.1062058-5-ruifeng.wang@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210108082523.1062058-1-ruifeng.wang@arm.com> References: <20201218101210.356836-1-ruifeng.wang@arm.com> <20210108082523.1062058-1-ruifeng.wang@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] [PATCH v2 4/5] common/octeontx2: fix build with sve enabled X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Building with gcc 10.2 with SVE extension enabled got error: {standard input}: Assembler messages: {standard input}:4002: Error: selected processor does not support `mov z3.b,#0' {standard input}:4003: Error: selected processor does not support `whilelo p1.b,xzr,x7' {standard input}:4005: Error: selected processor does not support `ld1b z0.b,p1/z,[x8]' {standard input}:4006: Error: selected processor does not support `whilelo p4.s,wzr,w7' This is because inline assembly code explicitly resets cpu model to not have SVE support. Thus SVE instructions generated by compiler auto vectorization got rejected by assembler. Fixed the issue by replacing inline assembly with equivalent atomic built-ins. Compiler will generate LSE instructions for cpu that has the extension. Fixes: 8a4f835971f5 ("common/octeontx2: add IO handling APIs") Cc: jerinj@marvell.com Cc: stable@dpdk.org Signed-off-by: Ruifeng Wang --- drivers/common/octeontx2/otx2_io_arm64.h | 37 +++--------------------- 1 file changed, 4 insertions(+), 33 deletions(-) diff --git a/drivers/common/octeontx2/otx2_io_arm64.h b/drivers/common/octeontx2/otx2_io_arm64.h index b5c85d9a6..8843a79b5 100644 --- a/drivers/common/octeontx2/otx2_io_arm64.h +++ b/drivers/common/octeontx2/otx2_io_arm64.h @@ -24,55 +24,26 @@ static __rte_always_inline uint64_t otx2_atomic64_add_nosync(int64_t incr, int64_t *ptr) { - uint64_t result; - /* Atomic add with no ordering */ - asm volatile ( - ".cpu generic+lse\n" - "ldadd %x[i], %x[r], [%[b]]" - : [r] "=r" (result), "+m" (*ptr) - : [i] "r" (incr), [b] "r" (ptr) - : "memory"); - return result; + return (uint64_t)__atomic_fetch_add(ptr, incr, __ATOMIC_RELAXED); } static __rte_always_inline uint64_t otx2_atomic64_add_sync(int64_t incr, int64_t *ptr) { - uint64_t result; - - /* Atomic add with ordering */ - asm volatile ( - ".cpu generic+lse\n" - "ldadda %x[i], %x[r], [%[b]]" - : [r] "=r" (result), "+m" (*ptr) - : [i] "r" (incr), [b] "r" (ptr) - : "memory"); - return result; + return (uint64_t)__atomic_fetch_add(ptr, incr, __ATOMIC_ACQUIRE); } static __rte_always_inline uint64_t otx2_lmt_submit(rte_iova_t io_address) { - uint64_t result; - - asm volatile ( - ".cpu generic+lse\n" - "ldeor xzr,%x[rf],[%[rs]]" : - [rf] "=r"(result): [rs] "r"(io_address)); - return result; + return __atomic_fetch_xor((uint64_t *)io_address, 0, __ATOMIC_RELAXED); } static __rte_always_inline uint64_t otx2_lmt_submit_release(rte_iova_t io_address) { - uint64_t result; - - asm volatile ( - ".cpu generic+lse\n" - "ldeorl xzr,%x[rf],[%[rs]]" : - [rf] "=r"(result) : [rs] "r"(io_address)); - return result; + return __atomic_fetch_xor((uint64_t *)io_address, 0, __ATOMIC_RELEASE); } static __rte_always_inline void -- 2.25.1