From: Wenjun Wu <wenjun1.wu@intel.com>
To: dev@dpdk.org, jia.guo@intel.com, qi.z.zhang@intel.com
Cc: Wenjun Wu <wenjun1.wu@intel.com>, stable@dpdk.org
Subject: [dpdk-stable] [PATCH v1] net/e1000: fix the invalid flow control mode setting
Date: Mon, 18 Jan 2021 15:33:45 +0800 [thread overview]
Message-ID: <20210118073345.61679-1-wenjun1.wu@intel.com> (raw)
E1000_CTRL register should be updated according to fc_conf->mode's value.
Fixes: af75078fece3 ("first public release")
Cc: stable@dpdk.org
Signed-off-by: Wenjun Wu <wenjun1.wu@intel.com>
---
drivers/net/e1000/igb_ethdev.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c
index 647aa8d99..390737393 100644
--- a/drivers/net/e1000/igb_ethdev.c
+++ b/drivers/net/e1000/igb_ethdev.c
@@ -3064,6 +3064,7 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
uint32_t rx_buf_size;
uint32_t max_high_water;
uint32_t rctl;
+ uint32_t ctrl;
hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
if (fc_conf->autoneg != hw->mac.autoneg)
@@ -3101,6 +3102,15 @@ eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
rctl &= ~E1000_RCTL_PMCF;
E1000_WRITE_REG(hw, E1000_RCTL, rctl);
+
+ ctrl = E1000_READ_REG(hw, E1000_CTRL);
+ ctrl &= ~(E1000_CTRL_RFCE|E1000_CTRL_TFCE);
+ if (fc_conf->mode == RTE_FC_RX_PAUSE || fc_conf->mode == RTE_FC_FULL)
+ ctrl |= E1000_CTRL_RFCE;
+ if (fc_conf->mode == RTE_FC_TX_PAUSE || fc_conf->mode == RTE_FC_FULL)
+ ctrl |= E1000_CTRL_TFCE;
+ E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
+
E1000_WRITE_FLUSH(hw);
return 0;
--
2.25.1
next reply other threads:[~2021-01-19 19:46 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-18 7:33 Wenjun Wu [this message]
2021-01-19 6:58 Wenjun Wu
2021-01-19 7:43 ` Guo, Jia
2021-01-20 4:58 Wenjun Wu
2021-01-20 5:55 ` Guo, Jia
2021-01-20 6:53 Wenjun Wu
2021-01-20 7:18 ` Guo, Jia
2021-01-20 23:35 ` Zhang, Qi Z
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