From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id DAED0A0547 for ; Tue, 9 Feb 2021 11:35:55 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id D519A16070A; Tue, 9 Feb 2021 11:35:55 +0100 (CET) Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) by mails.dpdk.org (Postfix) with ESMTP id 3236E16070A for ; Tue, 9 Feb 2021 11:35:54 +0100 (CET) Received: by mail-wm1-f44.google.com with SMTP id j21so2975528wmj.0 for ; Tue, 09 Feb 2021 02:35:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0tCjHi+hXJ5ns1IgyixVxqzwQ7keBZ/WgVCFeY6tkmA=; b=H9dzR2xf/pg42VvuqmmUxM3sd8GRUcc3gmhtjdc/UDF2HK2xpLoX5Zd4/D8sm3V//Q tyTBcMXmGtLsC2wxsstPbPUhtl1G9FXqPMFJeqJgCFYvxiXZfLqrTaOG6ZiB5Jdo50Jl O3lx4TyFJ0FTbGw65VS3Hfn7W7DqKe/Q5ge7O42Xk5O1uKHRbL0bdhsYJuBmH5Ok9WhM CFNz960oLfaPsv1HzbCJ5FLPIgfzWFpxpxChZFPrDpif9JihVjRAiRa8nNjbFRr/Vf3g Ok2m5LtKN6zJAdUz3UA2PO2P3ch0CxT/DhIPlWJQjhvlyr70qlZHq/0zRwU44P9cvp2Q kiLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0tCjHi+hXJ5ns1IgyixVxqzwQ7keBZ/WgVCFeY6tkmA=; b=ue0WS8y58l1n92r00q+6NUv8IkWVRfzLjIh8nb3eQXuescvGvWOt0ndzxlRG3BeHyg T/PHybt9jCaeM4lOFEGzzge2dwCoR4ZrOZmUlYU8BM1GbyjseWWFb1ZlZDYf7tK85ARt 8DgtOWUV1PGyz0C0No1xgGIZjUbrqe7+wqzQ2n5a0Bvlz/PYaE87R9O46tDx4CIF0PTR boa8pzef4hLbDLfZ3IImjTd4cluMrQWG3A5KjnV08nW3kHYDQwfgsjyf1tlan3PfHBpi yD6s0pwsXg03FU4rpnGbspzzBSqSPYP3sFexjGH+1eA1R8OM1Jegr/2+j5HW8/GeFYoL e6Qw== X-Gm-Message-State: AOAM532aJCBfyUoAEDxvqFHIhRTBUjHHxtoZ3whBnlDekWHWyRxexc2C EAm3adglzMipWWaS6IgjnGqx7mmKRZz0YA== X-Google-Smtp-Source: ABdhPJxli5XkRwYga7PsxYSA3JkI1tUE9/WwEDsWgou2euo7aHJJT5nJYHrXhT1f4nM5P5RJuPTF8w== X-Received: by 2002:a1c:2311:: with SMTP id j17mr2795150wmj.38.1612866953970; Tue, 09 Feb 2021 02:35:53 -0800 (PST) Received: from localhost ([88.98.246.218]) by smtp.gmail.com with ESMTPSA id b138sm3705335wmb.35.2021.02.09.02.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Feb 2021 02:35:52 -0800 (PST) From: luca.boccassi@gmail.com To: Alexander Kozyrev Cc: Viacheslav Ovsiienko , dpdk stable Date: Tue, 9 Feb 2021 10:35:06 +0000 Message-Id: <20210209103529.466775-8-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210209103529.466775-1-luca.boccassi@gmail.com> References: <20210205111920.1272063-1-luca.boccassi@gmail.com> <20210209103529.466775-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] patch 'net/mlx5: check FW miniCQE format capabilities' has been queued to stable release 20.11.1 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.1 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 02/11/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/de75752e7e707382086c7d0e88b4946b6e9ca7bf Thanks. Luca Boccassi --- >From de75752e7e707382086c7d0e88b4946b6e9ca7bf Mon Sep 17 00:00:00 2001 From: Alexander Kozyrev Date: Tue, 2 Feb 2021 02:07:37 +0000 Subject: [PATCH] net/mlx5: check FW miniCQE format capabilities [ upstream commit 3d3f4e6d1aaaec77016a8b406371f1b491ae9044 ] miniCQE formats for Flow Tag and L3/L4 Header compression are only supported by Mellanox FW starting version 16.29.392. There is no point to allow user to enable these formats if FW cannot provide them. Check FW capabilities and deny user requests if the selected miniCQE format is not supported by an underlying NIC. Fixes: 54c2d46b160f ("net/mlx5: support flow tag and packet header miniCQEs") Signed-off-by: Alexander Kozyrev Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 5 +++++ drivers/common/mlx5/mlx5_devx_cmds.h | 3 +++ drivers/common/mlx5/mlx5_prm.h | 5 ++++- drivers/net/mlx5/linux/mlx5_os.c | 32 ++++++++++++++++++---------- 4 files changed, 33 insertions(+), 12 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index a0277b7cc0..eafee65f22 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -720,6 +720,11 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); + attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression); + attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr, + mini_cqe_resp_flow_tag); + attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr, + mini_cqe_resp_l3_l4_tag); if (attr->qos.sup) { MLX5_SET(query_hca_cap_in, in, op_mod, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index bddeabf0ea..78202eba9d 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -115,6 +115,9 @@ struct mlx5_hca_attr { uint32_t regex:1; uint32_t regexp_num_of_engines; uint32_t log_max_ft_sampler_num:8; + uint32_t cqe_compression:1; + uint32_t mini_cqe_resp_flow_tag:1; + uint32_t mini_cqe_resp_l3_l4_tag:1; struct mlx5_hca_qos_attr qos; struct mlx5_hca_vdpa_attr vdpa; }; diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 6f5e5dc5f6..00b425ac85 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1364,7 +1364,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 num_of_uars_per_page[0x20]; u8 flex_parser_protocols[0x20]; u8 reserved_at_560[0x20]; - u8 reserved_at_580[0x3c]; + u8 reserved_at_580[0x39]; + u8 mini_cqe_resp_l3_l4_tag[0x1]; + u8 mini_cqe_resp_flow_tag[0x1]; + u8 enhanced_cqe_compression[0x1]; u8 mini_cqe_resp_stride_index[0x1]; u8 cqe_128_always[0x1]; u8 cqe_compression_128[0x1]; diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index a055a8dd1c..91001473b0 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -670,7 +670,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, int err = 0; unsigned int hw_padding = 0; unsigned int mps; - unsigned int cqe_comp; unsigned int tunnel_en = 0; unsigned int mpls_en = 0; unsigned int swp = 0; @@ -862,12 +861,8 @@ err_secondary: mprq_caps.max_single_wqe_log_num_of_strides; } #endif - if (RTE_CACHE_LINE_SIZE == 128 && - !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) - cqe_comp = 0; - else - cqe_comp = 1; - config->cqe_comp = cqe_comp; + /* Rx CQE compression is enabled by default. */ + config->cqe_comp = 1; #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { tunnel_en = ((dv_attr.tunnel_offloads_caps & @@ -1098,10 +1093,6 @@ err_secondary: config->mps == MLX5_MPW_ENHANCED ? "enhanced " : config->mps == MLX5_MPW ? "legacy " : "", config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); - if (config->cqe_comp && !cqe_comp) { - DRV_LOG(WARNING, "Rx CQE compression isn't supported"); - config->cqe_comp = 0; - } if (config->devx) { err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config->hca_attr); if (err) { @@ -1200,6 +1191,25 @@ err_secondary: } #endif } + if (config->cqe_comp && RTE_CACHE_LINE_SIZE == 128 && + !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) { + DRV_LOG(WARNING, "Rx CQE 128B compression is not supported"); + config->cqe_comp = 0; + } + if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && + (!config->devx || !config->hca_attr.mini_cqe_resp_flow_tag)) { + DRV_LOG(WARNING, "Flow Tag CQE compression" + " format isn't supported."); + config->cqe_comp = 0; + } + if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && + (!config->devx || !config->hca_attr.mini_cqe_resp_l3_l4_tag)) { + DRV_LOG(WARNING, "L3/L4 Header CQE compression" + " format isn't supported."); + config->cqe_comp = 0; + } + DRV_LOG(DEBUG, "Rx CQE compression is %ssupported", + config->cqe_comp ? "" : "not "); if (config->tx_pp) { DRV_LOG(DEBUG, "Timestamp counter frequency %u kHz", config->hca_attr.dev_freq_khz); -- 2.29.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-02-09 10:34:58.237342958 +0000 +++ 0008-net-mlx5-check-FW-miniCQE-format-capabilities.patch 2021-02-09 10:34:57.866583151 +0000 @@ -1 +1 @@ -From 3d3f4e6d1aaaec77016a8b406371f1b491ae9044 Mon Sep 17 00:00:00 2001 +From de75752e7e707382086c7d0e88b4946b6e9ca7bf Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 3d3f4e6d1aaaec77016a8b406371f1b491ae9044 ] + @@ -13 +14,0 @@ -Cc: stable@dpdk.org @@ -25 +26 @@ -index b075af9f6d..cc70c794e7 100644 +index a0277b7cc0..eafee65f22 100644 @@ -28,4 +29,4 @@ -@@ -744,6 +744,11 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, - log_compress_mmo_size); - attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr, - log_decompress_mmo_size); +@@ -720,6 +720,11 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, + attr->flow_hit_aso = !!(MLX5_GET64(cmd_hca_cap, hcattr, + general_obj_types) & + MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO); @@ -41 +42 @@ -index 3e2a0a24f9..9dcd917c39 100644 +index bddeabf0ea..78202eba9d 100644 @@ -44 +45,2 @@ -@@ -126,6 +126,9 @@ struct mlx5_hca_attr { +@@ -115,6 +115,9 @@ struct mlx5_hca_attr { + uint32_t regex:1; @@ -47 +48,0 @@ - uint32_t geneve_tlv_opt; @@ -53 +54 @@ - int log_max_qp_sz; + }; @@ -55 +56 @@ -index 751dda2537..de721aa177 100644 +index 6f5e5dc5f6..00b425ac85 100644 @@ -58,6 +59,6 @@ -@@ -1444,7 +1444,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { - u8 max_geneve_tlv_options[0x8]; - u8 reserved_at_568[0x3]; - u8 max_geneve_tlv_option_data_len[0x5]; -- u8 reserved_at_570[0x4c]; -+ u8 reserved_at_570[0x49]; +@@ -1364,7 +1364,10 @@ struct mlx5_ifc_cmd_hca_cap_bits { + u8 num_of_uars_per_page[0x20]; + u8 flex_parser_protocols[0x20]; + u8 reserved_at_560[0x20]; +- u8 reserved_at_580[0x3c]; ++ u8 reserved_at_580[0x39]; @@ -71 +72 @@ -index 9b95b9fe31..2dc079779d 100644 +index a055a8dd1c..91001473b0 100644 @@ -74 +75 @@ -@@ -676,7 +676,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, +@@ -670,7 +670,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, @@ -82 +83 @@ -@@ -868,12 +867,8 @@ err_secondary: +@@ -862,12 +861,8 @@ err_secondary: @@ -97 +98 @@ -@@ -1104,10 +1099,6 @@ err_secondary: +@@ -1098,10 +1093,6 @@ err_secondary: @@ -108 +109 @@ -@@ -1206,6 +1197,25 @@ err_secondary: +@@ -1200,6 +1191,25 @@ err_secondary: