Depending on kernel capabilities and rdma-core version the mapping of UAR (User Access Region) of desired memory caching type (non-cached or write combining). The PMD implements the flexible strategy of UAR mapping, alternating the type of caching to succeed. During this process the failure diagnostics messages are emitted. These message are merely diagnostics ones and the logging level should be lowered to DEBUG. Fixes: a0bfe9d56f74 ("net/mlx5: fix UAR memory mapping type") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com> --- drivers/net/mlx5/mlx5.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index aae2ef9af7..4ee0005a5c 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -768,7 +768,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * the UAR mapping type into account on UAR setup * on queue creation. */ - DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)"); + DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; sh->tx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -781,7 +781,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * If Verbs/kernel does not support "Non-Cached" * try the "Write-Combining". */ - DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)"); + DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF; sh->tx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -800,7 +800,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * IB device context, on context closure all UARs * will be freed, should be no memory/object leakage. */ - DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR"); + DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR"); sh->tx_uar = NULL; } /* Check whether we finally succeeded with valid UAR allocation. */ @@ -821,7 +821,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * should be no datapath noticeable impact, * can try "Non-Cached" mapping safely. */ - DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)"); + DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; sh->devx_rx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -840,7 +840,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * IB device context, on context closure all UARs * will be freed, should be no memory/object leakage. */ - DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR"); + DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR"); sh->devx_rx_uar = NULL; } /* Check whether we finally succeeded with valid UAR allocation. */ -- 2.18.1
From: Viacheslav Ovsiienko
> Depending on kernel capabilities and rdma-core version the mapping of UAR
> (User Access Region) of desired memory caching type (non-cached or write
> combining). The PMD implements the flexible strategy of UAR mapping,
> alternating the type of caching to succeed. During this process the failure
> diagnostics messages are emitted. These message are merely diagnostics ones
> and the logging level should be lowered to DEBUG.
>
> Fixes: a0bfe9d56f74 ("net/mlx5: fix UAR memory mapping type")
> Cc: stable@dpdk.org
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Depending on kernel capabilities and rdma-core version the mapping of UAR (User Access Region) of desired memory caching type (non-cached or write combining) might fail. The PMD implements the flexible strategy of UAR mapping, alternating the type of caching to succeed. During this process the failure diagnostics messages are emitted. These messages are merely diagnostics ones and the logging level should be adjusted to DEBUG. Fixes: a0bfe9d56f74 ("net/mlx5: fix UAR memory mapping type") Cc: stable@dpdk.org Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com> --- v2: commit messahe typos fix --- drivers/net/mlx5/mlx5.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index aae2ef9af7..4ee0005a5c 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -768,7 +768,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * the UAR mapping type into account on UAR setup * on queue creation. */ - DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)"); + DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; sh->tx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -781,7 +781,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * If Verbs/kernel does not support "Non-Cached" * try the "Write-Combining". */ - DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)"); + DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF; sh->tx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -800,7 +800,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * IB device context, on context closure all UARs * will be freed, should be no memory/object leakage. */ - DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR"); + DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR"); sh->tx_uar = NULL; } /* Check whether we finally succeeded with valid UAR allocation. */ @@ -821,7 +821,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * should be no datapath noticeable impact, * can try "Non-Cached" mapping safely. */ - DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)"); + DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; sh->devx_rx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -840,7 +840,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * IB device context, on context closure all UARs * will be freed, should be no memory/object leakage. */ - DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR"); + DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR"); sh->devx_rx_uar = NULL; } /* Check whether we finally succeeded with valid UAR allocation. */ -- 2.18.1
Hi,
> -----Original Message-----
> From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Sent: Monday, February 22, 2021 5:45 PM
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; stable@dpdk.org
> Subject: [PATCH] net/mlx5: fix UAR allocation diagnostics messages
>
> Depending on kernel capabilities and rdma-core version the mapping
> of UAR (User Access Region) of desired memory caching type (non-cached
> or write combining). The PMD implements the flexible strategy of
> UAR mapping, alternating the type of caching to succeed. During
> this process the failure diagnostics messages are emitted. These
> message are merely diagnostics ones and the logging level should be
> lowered to DEBUG.
>
> Fixes: a0bfe9d56f74 ("net/mlx5: fix UAR memory mapping type")
> Cc: stable@dpdk.org
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
Hi,
> -----Original Message-----
> From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Sent: Wednesday, February 24, 2021 10:18 AM
> To: dev@dpdk.org
> Cc: Raslan Darawsheh <rasland@nvidia.com>; Matan Azrad
> <matan@nvidia.com>; stable@dpdk.org
> Subject: [PATCH v2] net/mlx5: fix UAR allocation diagnostics messages
>
> Depending on kernel capabilities and rdma-core version the mapping
> of UAR (User Access Region) of desired memory caching type (non-cached
> or write combining) might fail. The PMD implements the flexible
> strategy of UAR mapping, alternating the type of caching to succeed.
> During this process the failure diagnostics messages are emitted.
> These messages are merely diagnostics ones and the logging level
> should be adjusted to DEBUG.
>
> Fixes: a0bfe9d56f74 ("net/mlx5: fix UAR memory mapping type")
> Cc: stable@dpdk.org
>
> Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
>
> ---
> v2: commit messahe typos fix
> ---
Sent previous reply to wrong version mail,
The correct version which is applied is v2.
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh