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From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: dev@dpdk.org
Cc: rasland@nvidia.com, matan@nvidia.com, orika@nvidia.com, stable@dpdk.org
Subject: [dpdk-stable] [PATCH v3 2/5] net/mlx5: add timestamp format support
Date: Sun, 14 Mar 2021 12:12:59 +0000
Message-ID: <20210314121302.5988-3-viacheslavo@nvidia.com> (raw)
In-Reply-To: <20210314121302.5988-1-viacheslavo@nvidia.com>

This patch adds support for the timestamp format settings for
the receive and send queues. If the firmware version x.30.1000
or above is installed and the NIC timestamps are configured
with the real-time format, the default zero values for newly
added fields cause the queue creation to fail.

The patch queries the timestamp formats supported by the hardware
and sets the configuration values in queue context accordingly.

Fixes: 86fc67fc9315 ("net/mlx5: create advanced RxQ object via DevX")
Fixes: ae18a1ae9692 ("net/mlx5: support Tx hairpin queues")
Fixes: 15c3807e86ab ("common/mlx5: support DevX QP operations")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
Acked-by: Ori Kam <orika@nvidia.com>
---
 drivers/net/mlx5/linux/mlx5_os.c   | 3 +++
 drivers/net/mlx5/mlx5.h            | 3 +++
 drivers/net/mlx5/mlx5_devx.c       | 2 +-
 drivers/net/mlx5/mlx5_flow_age.c   | 7 +++++--
 drivers/net/mlx5/mlx5_txpp.c       | 2 ++
 drivers/net/mlx5/windows/mlx5_os.c | 3 +++
 6 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 81eb2e4b05..dca3f92da7 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -1162,6 +1162,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
 			sh->cmng.relaxed_ordering_read = 0;
 			sh->cmng.relaxed_ordering_write = 0;
 		}
+		sh->rq_ts_format = config->hca_attr.rq_ts_format;
+		sh->sq_ts_format = config->hca_attr.sq_ts_format;
+		sh->qp_ts_format = config->hca_attr.qp_ts_format;
 		/* Check for LRO support. */
 		if (config->dest_tir && config->hca_attr.lro_cap &&
 		    config->dv_flow_en) {
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index a281fd20ea..14043b68d3 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -681,6 +681,9 @@ struct mlx5_dev_ctx_shared {
 	uint16_t bond_dev; /* Bond primary device id. */
 	uint32_t devx:1; /* Opened with DV. */
 	uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */
+	uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */
+	uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */
+	uint32_t qp_ts_format:2; /* QP timestamp formats supported. */
 	uint32_t max_port; /* Maximal IB device port index. */
 	void *ctx; /* Verbs/DV/DevX context. */
 	void *pd; /* Protection Domain. */
diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index 2cb3bd1f12..5c940edd88 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -996,8 +996,8 @@ mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,
 			.uar_page =
 				 mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),
 		},
+		.ts_format = mlx5_ts_format_conv(priv->sh->sq_ts_format),
 	};
-
 	/* Create Send Queue object with DevX. */
 	return mlx5_devx_sq_create(priv->sh->ctx, &txq_obj->sq_obj, log_desc_n,
 				   &sq_attr, priv->sh->numa_node);
diff --git a/drivers/net/mlx5/mlx5_flow_age.c b/drivers/net/mlx5/mlx5_flow_age.c
index 3005afdd33..00cb20dd62 100644
--- a/drivers/net/mlx5/mlx5_flow_age.c
+++ b/drivers/net/mlx5/mlx5_flow_age.c
@@ -202,7 +202,8 @@ mlx5_aso_init_sq(struct mlx5_aso_sq *sq)
  */
 static int
 mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
-		   void *uar, uint32_t pdn,  uint16_t log_desc_n)
+		   void *uar, uint32_t pdn,  uint16_t log_desc_n,
+		   uint32_t ts_format)
 {
 	struct mlx5_devx_create_sq_attr attr = {
 		.user_index = 0xFFFF,
@@ -210,6 +211,7 @@ mlx5_aso_sq_create(void *ctx, struct mlx5_aso_sq *sq, int socket,
 			.pd = pdn,
 			.uar_page = mlx5_os_get_devx_uar_page_id(uar),
 		},
+		.ts_format = mlx5_ts_format_conv(ts_format),
 	};
 	struct mlx5_devx_modify_sq_attr modify_attr = {
 		.state = MLX5_SQC_STATE_RDY,
@@ -265,7 +267,8 @@ int
 mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh)
 {
 	return mlx5_aso_sq_create(sh->ctx, &sh->aso_age_mng->aso_sq, 0,
-				  sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC);
+				  sh->tx_uar, sh->pdn, MLX5_ASO_QUEUE_LOG_DESC,
+				  sh->sq_ts_format);
 }
 
 /**
diff --git a/drivers/net/mlx5/mlx5_txpp.c b/drivers/net/mlx5/mlx5_txpp.c
index 696282ca31..e8d632ad23 100644
--- a/drivers/net/mlx5/mlx5_txpp.c
+++ b/drivers/net/mlx5/mlx5_txpp.c
@@ -234,6 +234,7 @@ mlx5_txpp_create_rearm_queue(struct mlx5_dev_ctx_shared *sh)
 			.pd = sh->pdn,
 			.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
 		},
+		.ts_format = mlx5_ts_format_conv(sh->sq_ts_format),
 	};
 	struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
 	struct mlx5_devx_cq_attr cq_attr = {
@@ -443,6 +444,7 @@ mlx5_txpp_create_clock_queue(struct mlx5_dev_ctx_shared *sh)
 	sq_attr.wq_attr.cd_slave = 1;
 	sq_attr.wq_attr.uar_page = mlx5_os_get_devx_uar_page_id(sh->tx_uar);
 	sq_attr.wq_attr.pd = sh->pdn;
+	sq_attr.ts_format = mlx5_ts_format_conv(sh->sq_ts_format);
 	ret = mlx5_devx_sq_create(sh->ctx, &wq->sq_obj, log2above(wq->sq_size),
 				  &sq_attr, sh->numa_node);
 	if (ret) {
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index e37cc65c17..d73a0d1502 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -497,6 +497,9 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
 						 (NS_PER_S / MS_PER_S))
 				config->rt_timestamp = 1;
 		}
+		sh->rq_ts_format = config->hca_attr.rq_ts_format;
+		sh->sq_ts_format = config->hca_attr.sq_ts_format;
+		sh->qp_ts_format = config->hca_attr.qp_ts_format;
 	}
 	if (config->mprq.enabled) {
 		DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
-- 
2.28.0


  parent reply	other threads:[~2021-03-14 12:13 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20210307100251.22538-1-viacheslavo@nvidia.com>
2021-03-07 10:02 ` [dpdk-stable] [PATCH 1/5] common/mlx5: add timestamp format support to DevX Viacheslav Ovsiienko
2021-03-11 19:36   ` Matan Azrad
2021-03-07 10:02 ` [dpdk-stable] [PATCH 2/5] net/mlx5: add timestamp format support Viacheslav Ovsiienko
2021-03-11 19:52   ` Matan Azrad
2021-03-07 10:02 ` [dpdk-stable] [PATCH 3/5] vdpa/mlx5: " Viacheslav Ovsiienko
2021-03-11 19:55   ` Matan Azrad
2021-03-07 10:02 ` [dpdk-stable] [PATCH 4/5] regex/mlx5: " Viacheslav Ovsiienko
2021-03-11 19:56   ` Matan Azrad
2021-03-07 10:02 ` [dpdk-stable] [PATCH 5/5] compress/mlx5: " Viacheslav Ovsiienko
2021-03-11 19:56   ` Matan Azrad
     [not found] ` <20210314115803.3110-1-viacheslavo@nvidia.com>
2021-03-14 11:57   ` [dpdk-stable] [PATCH 1/5] common/mlx5: add timestamp format support to DevX Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 2/5] net/mlx5: add timestamp format support Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 3/5] vdpa/mlx5: " Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 4/5] regex/mlx5: " Viacheslav Ovsiienko
2021-03-14 11:58   ` [dpdk-stable] [PATCH 5/5] compress/mlx5: " Viacheslav Ovsiienko
     [not found] ` <20210314121302.5988-1-viacheslavo@nvidia.com>
2021-03-14 12:12   ` [dpdk-stable] [PATCH v3 1/5] common/mlx5: add timestamp format support to DevX Viacheslav Ovsiienko
2021-03-14 12:12   ` Viacheslav Ovsiienko [this message]
2021-03-14 12:13   ` [dpdk-stable] [PATCH v3 3/5] vdpa/mlx5: add timestamp format support Viacheslav Ovsiienko
2021-03-14 12:13   ` [dpdk-stable] [PATCH v3 4/5] regex/mlx5: " Viacheslav Ovsiienko
2021-03-14 12:13   ` [dpdk-stable] [PATCH v3 5/5] compress/mlx5: " Viacheslav Ovsiienko

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