From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9AF5EA0548 for ; Sun, 9 May 2021 19:18:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 371C04110B; Sun, 9 May 2021 19:18:19 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C87DF410FE; Sun, 9 May 2021 19:18:16 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 149HFofE022329; Sun, 9 May 2021 10:18:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=a7Ky6XdMyAl+8Wu0osx86eIe20rU3uB/mQrwVdqnJjo=; b=fFnzUSjg3/onrepZbhR8cHMpVLZQLzhrwKoZjLfMhfe7HXbxLnyf5pri4e6T66MgkcrZ AAtzXU2lqK3SWQGPlvA7umAeSy2zJunQx7Fta3Y8qPJljqc6xClye8/R1c2pJoqoKoPC hGiCCAwvZMK8dMQEw0iqdr5tQBLH7taUl7lAuzfKGf8XoHxh31e8ku/TYzlYVs8oFj1h KHgpefBVutiey6jTfWxh7JdzlhVssjNmnllN4Ccty4tm6ZBYSnRISV1YzeGwoCV/jTQG T1ZyHD/qFILkzJxYuLzyJW5XpCIw9xB26x8hnpKU4h8dKgT2WDZ/b/klMHGPSQOWLGVm tA== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 38eg89gdve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 09 May 2021 10:18:15 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 9 May 2021 10:18:14 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 9 May 2021 10:18:14 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 50F775E6885; Sun, 9 May 2021 10:18:09 -0700 (PDT) From: To: , Haiyue Wang , "Jiawen Wu" , Jian Wang , "Thomas Monjalon" , Ferruh Yigit , "Andrew Rybchenko" CC: , Pavan Nikhilesh , Date: Sun, 9 May 2021 22:48:02 +0530 Message-ID: <20210509171803.1385-2-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210509171803.1385-1-pbhagavatula@marvell.com> References: <20210509171803.1385-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: bTQErNHuMn8f-VTknRHyukkk_o_2cHcA X-Proofpoint-ORIG-GUID: bTQErNHuMn8f-VTknRHyukkk_o_2cHcA X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-09_09:2021-05-06, 2021-05-09 signatures=0 Subject: [dpdk-stable] [dpdk-dev] [PATCH 2/2] eal: fix side effects in ptr align macros X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" From: Pavan Nikhilesh Avoid expanding parameters inside RTE_*_ALIGN macros. Update common_autotest to detect macro side effects. Workaround static arrays relying on RTE_ALIGN macros. Fixes: af75078fece3 ("first public release") Cc: stable@dpdk.org Signed-off-by: Pavan Nikhilesh Signed-off-by: David Marchand --- app/test/test_common.c | 6 ++++++ drivers/net/e1000/e1000_ethdev.h | 7 ++++--- drivers/net/ixgbe/ixgbe_ethdev.h | 6 ++++-- drivers/net/txgbe/txgbe_ethdev.h | 6 ++++-- lib/eal/include/rte_common.h | 17 +++++++++++++---- lib/ethdev/rte_eth_ctrl.h | 5 +++-- 6 files changed, 34 insertions(+), 13 deletions(-) diff --git a/app/test/test_common.c b/app/test/test_common.c index 0dbb87e741..9efe3b10f9 100644 --- a/app/test/test_common.c +++ b/app/test/test_common.c @@ -69,6 +69,12 @@ test_macros(int __rte_unused unused_parm) TEST_SIDE_EFFECT_2(RTE_PTR_ADD, void *, size_t); TEST_SIDE_EFFECT_2(RTE_PTR_DIFF, void *, void *); TEST_SIDE_EFFECT_2(RTE_PTR_SUB, void *, size_t); + TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN, void *, size_t); + TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN_CEIL, void *, size_t); + TEST_SIDE_EFFECT_2(RTE_PTR_ALIGN_FLOOR, void *, size_t); + TEST_SIDE_EFFECT_2(RTE_ALIGN, unsigned int, unsigned int); + TEST_SIDE_EFFECT_2(RTE_ALIGN_CEIL, unsigned int, unsigned int); + TEST_SIDE_EFFECT_2(RTE_ALIGN_FLOOR, unsigned int, unsigned int); TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_CEIL, unsigned int, unsigned int); TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_FLOOR, unsigned int, unsigned int); TEST_SIDE_EFFECT_2(RTE_ALIGN_MUL_NEAR, unsigned int, unsigned int); diff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h index 3b4d9c3ee6..155d825d89 100644 --- a/drivers/net/e1000/e1000_ethdev.h +++ b/drivers/net/e1000/e1000_ethdev.h @@ -332,9 +332,10 @@ struct igb_eth_syn_filter_ele { }; #define IGB_FLEX_FILTER_MAXLEN 128 /**< bytes to use in flex filter. */ -#define IGB_FLEX_FILTER_MASK_SIZE \ - (RTE_ALIGN(IGB_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT) - /**< mask bytes in flex filter. */ +#define IGB_FLEX_FILTER_MASK_SIZE \ + (RTE_ALIGN_FLOOR(IGB_FLEX_FILTER_MAXLEN + (CHAR_BIT - 1), CHAR_BIT) / \ + CHAR_BIT) +/**< mask bytes in flex filter. */ /** * A structure used to define the flex filter entry diff --git a/drivers/net/ixgbe/ixgbe_ethdev.h b/drivers/net/ixgbe/ixgbe_ethdev.h index a0ce18ca24..f2f8b943d2 100644 --- a/drivers/net/ixgbe/ixgbe_ethdev.h +++ b/drivers/net/ixgbe/ixgbe_ethdev.h @@ -311,8 +311,10 @@ struct ixgbe_5tuple_filter { uint16_t queue; /* rx queue assigned to */ }; -#define IXGBE_5TUPLE_ARRAY_SIZE \ - (RTE_ALIGN(IXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \ +#define IXGBE_5TUPLE_ARRAY_SIZE \ + (RTE_ALIGN_FLOOR(IXGBE_MAX_FTQF_FILTERS + (sizeof(uint32_t) * NBBY) - \ + 1, \ + (sizeof(uint32_t) * NBBY)) / \ (sizeof(uint32_t) * NBBY)) struct ixgbe_ethertype_filter { diff --git a/drivers/net/txgbe/txgbe_ethdev.h b/drivers/net/txgbe/txgbe_ethdev.h index 3021933965..05537b34c7 100644 --- a/drivers/net/txgbe/txgbe_ethdev.h +++ b/drivers/net/txgbe/txgbe_ethdev.h @@ -219,8 +219,10 @@ struct txgbe_5tuple_filter { uint16_t queue; /* rx queue assigned to */ }; -#define TXGBE_5TUPLE_ARRAY_SIZE \ - (RTE_ALIGN(TXGBE_MAX_FTQF_FILTERS, (sizeof(uint32_t) * NBBY)) / \ +#define TXGBE_5TUPLE_ARRAY_SIZE \ + (RTE_ALIGN_FLOOR(TXGBE_MAX_FTQF_FILTERS + (sizeof(uint32_t) * NBBY) - \ + 1, \ + (sizeof(uint32_t) * NBBY)) / \ (sizeof(uint32_t) * NBBY)) struct txgbe_ethertype_filter { diff --git a/lib/eal/include/rte_common.h b/lib/eal/include/rte_common.h index a142596587..6acd067b5c 100644 --- a/lib/eal/include/rte_common.h +++ b/lib/eal/include/rte_common.h @@ -294,8 +294,13 @@ static void __attribute__((destructor(RTE_PRIO(prio)), used)) func(void) * point to an address no lower than the first parameter. Second parameter * must be a power-of-two value. */ -#define RTE_PTR_ALIGN_CEIL(ptr, align) \ - RTE_PTR_ALIGN_FLOOR((typeof(ptr))RTE_PTR_ADD(ptr, (align) - 1), align) +#define RTE_PTR_ALIGN_CEIL(ptr, align) \ + __extension__({ \ + typeof(ptr) _pc = (ptr); \ + typeof(align) _ac = (align); \ + RTE_PTR_ALIGN_FLOOR((typeof(ptr))RTE_PTR_ADD(_pc, _ac - 1), \ + _ac); \ + }) /** * Macro to align a value to a given power-of-two. The resultant value @@ -303,8 +308,12 @@ static void __attribute__((destructor(RTE_PRIO(prio)), used)) func(void) * than the first parameter. Second parameter must be a power-of-two * value. */ -#define RTE_ALIGN_CEIL(val, align) \ - RTE_ALIGN_FLOOR(((val) + ((typeof(val)) (align) - 1)), align) +#define RTE_ALIGN_CEIL(val, align) \ + __extension__({ \ + typeof(val) _vc = (val); \ + typeof(val) _ac = (typeof(val))(align); \ + RTE_ALIGN_FLOOR((_vc + _ac - 1), _ac); \ + }) /** * Macro to align a pointer to a given power-of-two. The resultant diff --git a/lib/ethdev/rte_eth_ctrl.h b/lib/ethdev/rte_eth_ctrl.h index 42652f9cce..863e56170b 100644 --- a/lib/ethdev/rte_eth_ctrl.h +++ b/lib/ethdev/rte_eth_ctrl.h @@ -431,8 +431,9 @@ enum rte_fdir_mode { }; #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t)) -#define RTE_FLOW_MASK_ARRAY_SIZE \ - (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) +#define RTE_FLOW_MASK_ARRAY_SIZE \ + (RTE_ALIGN_FLOOR(RTE_ETH_FLOW_MAX + (UINT64_BIT - 1), UINT64_BIT) / \ + UINT64_BIT) /** * A structure used to get the information of flow director filter. -- 2.17.1